Miyama Masayuki | Kanazawa University Graduate School Of Natural Science & Technology
スポンサーリンク
概要
関連著者
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Miyama Masayuki
Kanazawa University Graduate School Of Natural Science & Technology
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Miyama M
Graduate School Of Natural Science And Technology Kanazawa University
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Yoshimoto Masahiko
Mitsubishi Electric Corporation
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Yoshimoto Masahiko
System Lsi Development Center Mitsubishi Electric Corporation
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Yoshimoto M
Department Of Computer Science And Systems Engineering Kobe University
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Morita Yasuhiro
Department Of Computer Science And Systems Engineering Kobe University
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MIYAKOSHI Junichi
Kobe University
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Yoshimoto Masahiko
Department Of Computer Science And Systems Engineering Kobe University
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Miyama Masayuki
Kanazawa Univ. Kanazawa‐shi Jpn
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MORITA Yasuhiro
Kobe University
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Matsuno Tetsuro
Kanazawa University Graduate School Of Natural Science & Technology
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Kawaguchi Hiroshi
Kobe Univ. Kobe‐shi Jpn
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Imamura Kousuke
The Dept. Of Electrical & Electronic System Kanazawa University
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Kawaguchi Hiroshi
Department Of Computer Science And Systems Engineering Kobe University
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Yoshimoto Masahiko
Faculty Of Engineering Kobe University
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MIYAKOSHI Junichi
Faculty of Engineering, Kobe University
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MIYAMA Masayuki
Faculty of Engineering, Kanazawa University
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Hashimoto H
The Dept. Of Electrical & Electronic System Kanazawa University
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Hashimoto Hideo
The Dept. Of Electrical & Electronic System Kanazawa University
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Miyama Masayuki
Graduate School of Natural Science, Kanazawa University
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Miyama Masayuki
Graduate School Of Natural Science And Technology Kanazawa Univ.
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Yamamoto Ryo
Kobe University
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FUKUYAMA Yuki
Kobe University
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MATSUDA Yoshio
Kanazawa University
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Hamano Koji
Faculty Of Engineering Kanazawa University
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KAWAKAMI Kentaro
Graduate School of Science and Technology, Kobe University
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MURACHI Yuichiro
Faculty of Engineering, Kanazawa University
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MATSUNO Tetsuro
Faculty of Engineering, Kanazawa University
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Kanamori M
Graduate School Of Natural Science And Technology Kanazawa University
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Kawakami Kentaro
Graduate School Of Science And Technology Kobe University
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Kato Ai
The Authors Are With The Faculty Of Engineering Kanazawa University
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Kawaguchi Hiroshi
Graduate School of Engineering, Kobe University
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Yoshimoto Masahiko
Graduate School of Engineering, Kobe University
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YOSHIMOTO Masahiko
Department of Computer Science and Systems Engineering, Kobe University
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YOSHIMOTO Masahiko
The authors are with Information Technology R&D Center, Mitsubishi Electric Corporation
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MIYAMA Masayuki
The authors are with the Faculty of Engineering, Kanazawa University
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TOOYAMA Osamu
The authors are with the Faculty of Engineering, Kanazawa University
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TAKAMATSU Naoki
The authors are with the Faculty of Engineering, Kanazawa University
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KODAKE Tsuyoshi
The authors are with the Faculty of Engineering, Kanazawa University
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NAKAMURA Kazuo
The authors are with the Faculty of Engineering, Kanazawa University
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MIYAKOSHI Junichi
The authors are with the Faculty of Engineering, Kanazawa University
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IMAMURA Kousuke
The authors are with the Faculty of Engineering, Kanazawa University
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HASHIMOTO Hideo
The authors are with the Faculty of Engineering, Kanazawa University
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KOMATSU Satoshi
The author is with VLSI Design and Education Center, The University of Tokyo
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YAGI Mikio
The authors are with the Faculty of Engineering, Kobe University
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MORIMOTO Masao
The authors are with the Faculty of Engineering, Kobe University
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TAKI Kazuo
The authors are with the Faculty of Engineering, Kobe University
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Tooyama Osamu
The Authors Are With The Faculty Of Engineering Kanazawa University
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Morimoto Masao
The Authors Are With The Faculty Of Engineering Kobe University
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Kodake Tsuyoshi
The Authors Are With The Faculty Of Engineering Kanazawa University
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Takamatsu Naoki
The Authors Are With The Faculty Of Engineering Kanazawa University
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Miyama Masayuki
Kanazawa University
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Komatsu Satoshi
The Author Is With Vlsi Design And Education Center The University Of Tokyo
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MURACHI Yuichiro
Kobe University
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ISHIHARA Hajime
Kanazawa University
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YOSHIMOTO Masahiko
Kobe University
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MINEGISHI Noriyuki
the Dept. of Electrical & Electronic System, Kanazawa University
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MIYAKOSHI Junichi
the Dept. of Computer ard Systems Engineering, Kobe University
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KURODA Yuki
the Dept. of Electrical & Electronic System, Kanazawa University
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KATAGIRI Tadayoshi
the Dept. of Electrical & Electronic System, Kanazawa University
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FUKUYAMA Yuki
the Dept. of Computer ard Systems Engineering, Kobe University
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YAMAMOTO Ryo
the Dept. of Computer ard Systems Engineering, Kobe University
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MIYAMA Masayuki
the Dept. of Electrical & Electronic System, Kanazawa University
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HASHIMOTO Hideo
the Dept. of Electrical & Electronic System, Kanazawa University
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YOSHIMOTO Masahiko
the Dept. of Computer ard Systems Engineering, Kobe University
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中尾 政史
株式会社ナナオ
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MIKAMI Shinji
Kanazawa University Graduate School of Natural Science & Technology
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MATSUNO Tetsuro
Kanazawa University Graduate School of Natural Science & Technology
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KAWAGUCHI Hiroshi
Computer and Systems Department Kobe University
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YOSHIMOTO Masahiko
Computer and Systems Department Kobe University
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ONO Hiroaki
Linear Circuit Corp.
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Matsuno Tetsuro
Graduate School Of System Informatics Kobe University
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Yagi Mikio
The Authors Are With The Faculty Of Engineering Kobe University
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Taki Kazuo
The Authors Are With The Faculty Of Engineering Kobe University
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Kuroda Yuki
The Dept. Of Electrical & Electronic System Kanazawa University:presently With Hitachi Ltd.
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Ohira Hideo
Kanazawa University
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Morita Yasuhiro
Graduate School Of Natural Science And Technology Kanazawa University
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HAMAMOTO Masaki
Kobe University
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IINUMA Takahiro
Kobe University
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ISHIHARA Tomokazu
Kobe University
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TAKEMURA Jun
Graduate School of Natural Science and Technology, Kanazawa University
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MIYAKOSHI Junichi
Graduate School of Science and Technology, Kobe University
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MURACHI Yuichiro
Graduate School of Science and Technology, Kobe University
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HAMAMOTO Masaki
Graduate School of Science and Technology, Kobe University
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IINUMA Takahiro
Graduate School of Science and Technology, Kobe University
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ISHIHARA Tomokazu
Graduate School of Science and Technology, Kobe University
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Mikami Shinji
Graduate School Of Science And Technology Kobe University
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Nakao Masashi
Eizo Nanao Co.
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KANAMORI Miwako
Graduate School of Natural Science and Technology, Kanazawa University
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IMAMURA Kousuke
Faculty of Engineering, Kanazawa University
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HASHIMOTO Hideo
Faculty of Engineering, Kanazawa University
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KAWAKAMI Kentaro
Kanazawa University
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KANAMORI Miwako
Kanazawa University
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MORITA Yasuhiro
Kanazawa University
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YOSHIMOTO Masahiko
Kanazawa University
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INOIE Yuusuke
Kanazawa University
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KASUGA Takafumi
Kanazawa University
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INADA Ryouichi
Kanazawa University
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Katagiri Tadayoshi
The Dept. Of Electrical & Electronic System Kanazawa University
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Minegishi Noriyuki
The Dept. Of Electrical & Electronic System Kanazawa University:information Technology R&d C
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Takemura Jun
Graduate School Of Natural Science And Technology Kanazawa University
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Yoshimoto Masahiko
The Department Of Electrical And Electric Engineering Kanazawa Univeresity
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Morita Yasuhiro
Graduate School Of Engineering Osaka University
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Ishihara Hajime
Kanazawa Univ. Kanazawa‐shi Jpn
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Nakamura Kazuo
The Authors Are With The Faculty Of Engineering Kanazawa University
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Murauchi Yuichiro
Faculty of Engineering, Kanazawa University
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Yoshimoto Masahiko
Department of Computer and Systems Engineering, Kobe University
著作論文
- VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
- A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
- An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
- A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
- VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
- An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
- A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
- A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
- A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
- Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
- A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission