A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, <Special Section>VLSI Design and CAD Algorithms)

スポンサーリンク

概要

• 論文の詳細を見る

• This paper describes a 95mW MPEG2 MP@HL motion estimation processor core for portable and high-resolution video applications such as that in an HD camcorder. It features a novel hierarchical algorithm and a low-power ring-connected systolic array architecture. It supports frame/field and bi-directional prediction with half-pel precision for 1920×1080@30 fps resolution video. The search range is ±128×±64 pixels. The ME core integrates 2.25M transistors in 3.1mm×3.1mm using 0.18-micron technology.

• 社団法人電子情報通信学会の論文
• 2005-12-01

著者

• Miyama Masayuki

  Kanazawa University Graduate School Of Natural Science & Technology

• Miyama M

  Graduate School Of Natural Science And Technology Kanazawa University

• Yoshimoto Masahiko

  Mitsubishi Electric Corporation

• Morita Yasuhiro

  Department Of Computer Science And Systems Engineering Kobe University

• MIYAKOSHI Junichi

  Kobe University

• Matsuno Tetsuro

  Kanazawa University Graduate School Of Natural Science & Technology

• Yoshimoto Masahiko

  Department Of Computer Science And Systems Engineering Kobe University

• Yoshimoto Masahiko

  System Lsi Development Center Mitsubishi Electric Corporation

• Yoshimoto Masahiko

  Faculty Of Engineering Kobe University

• Hamano Koji

  Faculty Of Engineering Kanazawa University

• MURACHI Yuichiro

  Faculty of Engineering, Kanazawa University

• MATSUNO Tetsuro

  Faculty of Engineering, Kanazawa University

• MIYAKOSHI Junichi

  Faculty of Engineering, Kobe University

• MIYAMA Masayuki

  Faculty of Engineering, Kanazawa University

• Yoshimoto M

  Department Of Computer Science And Systems Engineering Kobe University

• Murauchi Yuichiro

  Faculty of Engineering, Kanazawa University

関連論文

• An MPEG2 Video Decoder LSI with Hierarchical Control Mechanism
• A Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder with a 162MHz Media-processor Core and Dual Motion Estimation Cores
• Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
• An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
• VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding(Low-Power System LSI, IP and Related Technologies)
• A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU(Low-Power System LSI, IP and Related Technologies)
• An Ultra Low Power Motion Estimation Processor for MPEG2 HDTV Resolution Video
• Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock
• A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
• VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation (System LSIs and Microprocessors, VLSI Design Technology in the Sub-100nm Era)
• A Dependable SRAM with 7T/14T Memory Cells
• A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing
• Area Comparison between 6T and 8T SRAM Cells in Dual-V_ Scheme and DVS Scheme(Memory Design and Test,VLSI Design and CAD Algorithms)
• Area Optimization in 6T and 8T SRAM Cells Considering V_ Variation in Future Processes(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
• The Excellence of Aomori Hiba (Hinokiasunaro) in Its Use as Building Materials of Buddhist Temples and Shinto Shrines
• An Energy-Harvesting Wireless-Interface SoC for Short-Range Data Communication
• A 58-μW Single-Chip Sensor Node Processor with Communication Centric Design
• A power-variation model for sensor node and the impact against life time of wireless sensor networks
• A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks
• Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks
• A Sub 100mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
• Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks(Ubiquitous Sensor Networks)
• Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks(Mobile Multimedia Communications)
• A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
• A Highly Parallel DSP Architecture for Image Recognition
• A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline(VLSI Architecture,VLSI Design and CAD Algorithms)
• A sub-mW H.264 baseline-profile motion estimation processor core with a VLSI-oriented block partitioning strategy and SIMD/systolic-array architecture
• A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing(Novel Device Architectures and System Integration Technologies)
• A 95mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application(VLSI Architecture, VLSI Design and CAD Algorithms)
• A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation(Digital, Low-Power LSI and Low-Power IP)
• A Half-Pel Precision Motion Estimation Processor for NTSC-Resolution Video (Special Issue on Multimedia, Analog and Processing LSIs)
• Service Interval Optimization with Delay Bound Guarantee for HCCA in IEEE802.11e WLANs(Network)
• A New Scheduler to Guarantee Delay Bound with Bandwidth Optimization for HCCA in IEEE 802.11e WLANs(QoS及びトラヒック管理(2),ユビキタスネットワーク,モバイルネットワーク及び一般)
• Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era(Low Power Methodology, VLSI Design and CAD Algorithms)
• Future Technological and Economic Prospects for VLSI (Special Issue on LSI Memories)
• A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission
• A 0.3-V operating, Vth-variation-tolerant SRAM under DVS environment for memory-rich SoC in 90-nm technology era and beyond
• An Architectural Study of an MPEG-2 422P@HL Encoder Chip Set(Special Section on Digital Signal Processing)
• A Chip Set for Programmable Real-Time MPEG2 MP@ML Video Encoder(Special Issue on Multimedia, Network, and DRAM LSIs)
• ULSI Realization of MPEG2 Realtime Video Encoder and Decoder : An Overview
• A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition
• VLSI Architecture of GMM Processing and Viterbi Decoder for 60,000-Word Real-Time Continuous Speech Recognition
• A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
• Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes
• A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output
• 7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory
• A 0.15-μm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme
• A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme
• A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing
• A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI

もっと見る 閉じる

スポンサーリンク