A 158 MS/s JPEG 2000 Codec with a bit-plane and pass parallel embedded block coder for low delay image transmission
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概要
- 論文の詳細を見る
This paper describes a 158 MS/s JPEG 2000 codec with an embedded block coder (EBC) based on bit-plane and pass-parallel architecture. The EBC contains bit-plane coders (BPCs) corresponding to each bit-plane in a code-block. The upper and the lower bit-plane coding overlap in time with a 1-stripe and 1-column gap. The bit-modeling passes in the bit-plane coding also overlap in time with the same gap. These methods increase throughput by 30 times in comparison with the conventional. In addition, the methods support not only vertically causal mode, but also regular mode, which enhances the image quality. Furthermore, speculative decoding is adopted to increase throughput. This codec LSI was designed using 0.18/Limprocess. The core area is 4.7 x 4.7 mm2 and the frequency is 160 MHz. A system including the codec enables image transmission of PC desktop with 8 ms delay. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
- IEICE transactions on communications electronics information and systems = 電子情報通信学会の論文
- 2008-08-01
著者
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Miyama Masayuki
Kanazawa University Graduate School Of Natural Science & Technology
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Miyama Masayuki
Kanazawa Univ. Kanazawa‐shi Jpn
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Miyama Masayuki
Kanazawa University
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MATSUDA Yoshio
Kanazawa University
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中尾 政史
株式会社ナナオ
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Nakao Masashi
Eizo Nanao Co.
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INOIE Yuusuke
Kanazawa University
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KASUGA Takafumi
Kanazawa University
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INADA Ryouichi
Kanazawa University
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