0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme
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概要
- 論文の詳細を見る
This paper presents a novel cache architecture using 7T/14T SRAM, which can improve its reliability with control lines dynamically. Our proposed 14T word-enhancing scheme can enhance its operating margin in word granularity by combining two words in a low-voltage mode. Furthermore, we propose a new testing method that maximizes the efficiency of the 14T word-enhancing scheme. In a 65-nm process, it can reduce the minimum operation voltage (Vmin) to 0.5V to a level that is 42% and 21% lower, respectively, than those of a conventional 6T SRAM and a cache word-disable scheme. Measurement results show that the 14T word-enhancing scheme can reduce Vmin of the 6T SRAM and 14T dependable modes by 25% and 19%, respectively. The respective dynamic power reductions are 89.2% and 73.9%. The respective total power reductions are 44.8% and 20.9%.
著者
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Okumura Shunsuke
Graduate School of Engineering, Kobe University
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Kawaguchi Hiroshi
Graduate School of Engineering, Kobe University
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Yoshimoto Masahiko
Graduate School of Engineering, Kobe University
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Nakata Yohei
Graduate School of System Informatics, Kobe University
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Okumura Shunsuke
Graduate School of System Informatics, Kobe University
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