An FPGA Implementation of a HOG-based Object Detection Processor
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes a Histogram of Oriented Gradients (HOG)-based object detection processor. It features a simplified HOG algorithm with cell-based scanning and simultaneous Support Vector Machine (SVM) calculation, cell-based pipeline architecture, and parallelized modules. To evaluate the effectiveness of our approach, the proposed architecture is implemented onto a FPGA prototyping board. Results show that the proposed architecture can generate HOG features and detect objects with 40MHz for SVGA resolution video (800 × 600pixels) at 72 frames per second (fps).
著者
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Kawaguchi Hiroshi
Graduate School of Engineering, Kobe University
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Yoshimoto Masahiko
Graduate School of Engineering, Kobe University
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Takagi Kenta
Graduate School Of Engineering Tohoku University
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Izumi Shintaro
Graduate School of Engineering, Kobe University
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MlZUNO KOSUKE
Graduate School of Engineering, Kobe University
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TERACHI YOSUKE
Graduate School of Engineering, Kobe University
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