A VGA 30fps affine motion model estimation VLSI for real-time video segmentation

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概要

• 論文の詳細を見る

• This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0 × 5.0 mm2 in 0.18 μm process, standard cell technology. The ASIC can accommodate a VGA 30 fps video with 120 MHz clock frequency. Copyright© 2010.

• 2010-12-01

著者

• Matsuda Yoshio

  Graduate School of Natural Science, Kanazawa University

• Miyama Masayuki

  Graduate School Of Natural Science And Technology Kanazawa Univ.

• Miyama Masayuki

  Graduate School Of Natural Science And Technology Kanazawa University

• YUNBE Yoshiki

  Graduate School of Natural Science and Technology, Kanazawa University

• Yunbe Yoshiki

  Graduate School Of Natural Science And Technology Kanazawa University

• Matsuda Yoshio

  Graduate School Of Natural Science And Technology Kanazawa University

• Matsuda Yoshio

  Graduate School Of Natural Science And Technology Kanazawa Univ.

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