IWADE Shuhei | Osaka Institute of Technology

スポンサーリンク

概要

関連著者

もっと見る

著作論文

A Wide Range 1.0-3.6 V 200 Mbps, Push-Pull Output Buffer Using Parasitic Bipolar Transistors(Low-Power System LSI, IP and Related Technologies)
Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller
A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor(Special Issue on High-Performance and Low-Power Microprocessors)
Selective-Sets Resizable Cache Memory Design for High-Performance and Low-Power CPU Core(Low-Power System LSI, IP and Related Technologies)
A Low-Power Microcontroller with Body-Tied SOI Technology(Low-Power System LSI, IP and Related Technologies)
Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation(the IEEE International Conference on SISPAD '02)
Multimedia Accelerator ACE : A Practical Approach for Multimedia Applications

スポンサーリンク