Itoh Yoshio | Faculty Of Engineering Tottori University

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概要

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著作論文

Parallel Composition Based Adaptive Notch Filter : Performance and Analysis(Digital Signal Processing)
An Adaptive Algorithm for Cascaded Notch Filter with Reduced Bias
On the Necessity of Estimating the Transfer Level in an Allpass-FIR ADF by the Use of Lyapunov Criteria
A Newton Based Adaptive Algorithm for IIR ADF Using Allpass and FIR Filter
A Simple Algorithm for Adaptive Allpass-FIR Digital Filter Using Lattice Allpass Filter with Minimum Multipliers
A New Linear Prediction Filter Based Adaptive Algorithm For IIR ADF Using Allpass and Minimum Phase System
Robust DSP Type Squaring Loop withAdaptive Notch Filter Type Frequency Estimator and Adaptive BPF (Special Section on Noise Cancellation and Reduction Techniques)
A Study on Semi-Blind Adaptive equalizer for PSK and QPSK Signals
A Variable Step Size Algorithm for Speech Noise Reduction Method Based on Noise Reconstruction System
Two-microphone system using linear prediction and noise reconstruction
Method estimating reflection coefficients of adaptive lattice filter and its application to system identification
A Noise Reduction System for Wideband and Sinusoidal Noise Based on Adaptive Line Enhancer and Inverse Filter (Digital Signal Processing)
A Noise Reduction Method for Non-stationary Noise Based on Noise Reconstruction System with ALE(Digital Signal Processing)
A Noise Reduction Method Based on Linear Prediction Analysis
A New Noise Reduction Method Using Estimated Noise Spectrum(Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Threshold Equalization for On-Line Signature Verification
DWT Domain On-Line Signature Verification Using the Pen-Movement Vector(Information Security)
Speech Noise Reduction System Based on Frequency Domain ALE Using Windowed Modified DFT Pair(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Multi-Matcher On-Line Signature Verification System in DWT Domain(Information Hiding, Cryptography and Information Security)
Introduction of Orthonormal Transform into Neural Filter for Accelerating Convergence Speed(Special Section on Intelligent Signal and Image Processing)
Reduction of Computational Complexity in the IA Algorithm
Performance Analysis and Improvement of the NACF Algorithm (Special Section on Digital Signal Processing)
An Adaptive Algorithm with Variable Step-Size for Parallel Notch Filter (Digital Signal Processing)
A Noise Reduction Method Based on Linear Prediction with Variable Step-Size(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
PLL Frequency Synthesizer with Binary Phase Comparison (Special Section of Selected Papers from the 12th Workshop on Circuit and Systems in Karuizawa)
Prescaler PLL Frequency Synthesizer Introducing Multi-(N+1/2) Programmable Dividers
A New Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider
Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using a Target Frequency Detector (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
PLL Frequency Synthesizer with Multi-Phase Detector (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
A Multi-Loop PLL Frequency Synthesizer
Speedup of Frequency Switching Time in PLL Frequency Synthesizers Using Target Frequency Detector

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