W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory

スポンサーリンク

概要

• 論文の詳細を見る
• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2004-04-30

著者

• INUISHI Masahide

  Advanced Device Development Dept., Renesas Technology Corp.

• OHJI Yuzuru

  Advanced Device Development Dept., Renesas Technology Corp.

• Eimori Takahisa

  Advanced Device Development Department Renesas Technology Corporation

• Nishida Yukio

  Advanced Device Development Department Renesas Technology Corporation

• YAMASHITA Tomohiro

  Advanced Device Development Department, Renesas Technology Corporation

• HAYASHI Kiyoshi

  Advanced Device Development Department, Renesas Technology Corporation

関連論文

• Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application(Special Issue on Integrated Systems with New Concepts)
• Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
• Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
• W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory
• Scalability of Gate/N^- Overlapped Lightly Doped Drain in Deep-Submicrometer Regime
• Subquarter-micrometer Dual Gate Complementary Metal Oxide Semiconductor Field Effect Transistor with Ultrathin Gate Oxide of 2 nm
• Deep Submicron Field Isolation with Buried Insulator between Polysilicon Electrodes (BIPS) (Special Section on High Speed and High Density Multi Functional LSI Memories)
• Impact of Body Bias Controlling in Partially Depleted SOI Devices with Hybrid Trench Isolation Technology
• A 90nm-node SOI Technology for RF Applications
• Proximity Gettering of Heavy Metals by High-Energy Ion Implantation
• New P-MOSFET Hot-Carrier Degradation Model for Bi-Directional Operation
• Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs
• Advanced Retrograde Well Technology for 90-nm-Node Embedded Static Random Access Memory Using High-Energy Parallel Beam
• The Effects on Metal Oxide Semiconductor Field Effect Transistor Properties of Nitrogen Implantation into p^+ Polysilicon Gate
• The Impact of Nitrogen Implantation into Highty Doped Polysilicon Gates for flighty Reliable and High-Performance Sob-Quarter-Micron Dual-Gate Complementary Metal Oxide Semiconductor
• A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation (Special Issue on Sub-Half Micron Si Device and Process Technologies)
• W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory

もっと見る 閉じる

スポンサーリンク