Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs

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概要

• 論文の詳細を見る
• 社団法人応用物理学会の論文
• 1994-01-30

著者

• INUISHI Masahide

  ULSI Laboratory, Mitsubishi Electric Corporation

• TSUBOUCHI Natsuro

  ULSI Laboratory, Mitsubishi Electric Corporation

• INUISHI Masahide

  Advanced Device Development Dept., Renesas Technology Corp.

• KUROI Takashi

  ULSI Development Center, Mitsubishi Electric Corporation

• Tsukamoto K

  Univ. Tokyo Tokyo Jpn

• KINOSHITA Yoshitaka

  Department of Organic and Polymeric Materials, Tokyo Institute of Technology

• Tsubouchi Natsuro

  Lsi Research And Development Laboratory Mitusbishi Electric Corporation

• Tsubouchi Natsuro

  Ulsi Development Center Mitsubishi Electric Corporation

• Kuroi T

  Ulsi Development Center Mitsubishi Electric Corporation

• Kuroi Takashi

  Ulsi Development Center Mitsubishi Electric Corporation

• Kawasaki Y

  Mie Univ. Mie Jpn

• Kinoshita Yasushi

  ULSI Laboratory, Mitsubishi Electric Corporation

• Kinoshita Y

  Department Of Organic And Polymeric Materials Tokyo Institute Of Technology

• Kinoshita Yasushi

  Ulsi Laboratory Mitsubishi Electric Corporation

• Tsubouchi N

  Ulsi Dev. Center Hyogo Jpn

• Tsukamoto K

  Ulsi Laboratory Mitsubishi Electric Corporation

• KAWASAKI Youji

  ULSI Laboratory, Mitsubishi Electric Corporation

• ISHIGAKI Yoshiyuki

  ULSI Laboratory, Mitsubishi Electric Corporation

• TSUKAMOTO Katsuhiro

  ULSI Laboratory, Mitsubishi Electric Corporation

• Inuishi Masahide

  Advanced Device Development Dept. Renesas Technology Corp.

• Inuishi Masahide

  Ulsi Development Center Mitsubishi Electric Corporation

• Ishigaki Yoshiyuki

  Ulsi Laboratory Mitsubishi Electric Corporation

関連論文

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• Hydrogen Concentration and Bond Configurations in Silicon Nitride Films Prepared by ECR Plasma CVD Method
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• Direct Measurement of Transient Drain Currents in Partially-Depleted SOI N-Channel MOSFETs Using a Nuclear Microprobe for Highly Reliable Device Designs
• The Influence of the Buried Oxide Defects on the Gate Oxide Reliability and Drain Leakage Currents of the Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistors
• Low-Voltage Operation of a High-Resistivity Load SOI SRAM Cell by Reduced Back-Gate-Bias Effect
• Two-Dimensional Analytical Modeling of the Source/Drain Engineering Influemce on Short-Channel Effects in SOI MOSFET's
• Analytical Modeling of Short-Channel Behavior of Accumulation-Mode Transistors on Silicon-on-Insulator Substrate
• Suppression of Self-Heating in Hybrid Trench Isolated SOI MOSFETs with Poly-Si plug and W plug
• Saturation Phenomenon of Stress-Induced Gate Leakage Current
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• Proximity Gettering of Heavy Metals by High-Energy Ion Implantation
• New P-MOSFET Hot-Carrier Degradation Model for Bi-Directional Operation
• Application of Proximity Effect Correction Usirng Pattern-Area Density to Patterning on a Heavy-Metal Substrate and the Cell-Projection Exposure
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• Leakage Mechanism of Local Junctions Forming the Main or Tail Mode of Retention Characteristics for Dynamic Random Access Memories
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• Second-Harmonic Generation in Achiral Bent-Shaped Liquid Crystals
• Ferroelectricity in the Lyotropic Cholesteric Phase of Poly L-Glutamate
• Critical Current Density and Microstructure of Superconducting YBa_2Cu_3O Films Prepared by a Tape Casting Method : Electrical Properties Condensed Matter
• Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar-Complementary Metal Oxide Semiconductor LSIs
• Magnetic Detector Using Bi-Pb-Sr-Ca-Cu-O Superconductive Film
• Preparation of the High-T_c Superconductive Bi-Pb-Sr-Ca-Cu-O Film by Pyrolysis of Organic Acid Salts
• Novel Shallow Trench Isolation Process from Viewpoint of Total Strain Process Design for 45nm Node Devices and Beyond
• Advanced Retrograde Well Technology for 90-nm-Node Embedded Static Random Access Memory Using High-Energy Parallel Beam
• The Effects on Metal Oxide Semiconductor Field Effect Transistor Properties of Nitrogen Implantation into p^+ Polysilicon Gate
• Reliability of Source-to-Drain Non-Uniformly Doped Channel (NUDC)MOSFETs for Sub-Quarter-Micron Region
• Substrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiency
• Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors (MOSFETs) with Lightly Doped Drain Structure
• The Impact of Nitrogen Implantation into Highty Doped Polysilicon Gates for flighty Reliable and High-Performance Sob-Quarter-Micron Dual-Gate Complementary Metal Oxide Semiconductor
• A 0.4 μm Gate-All-Around TFT (GAT) Using a Dummy Nitride Pattern for High-Density Memories
• Quantum-Dot Logic Circuits Based on the Shared Binary-Decision Diagram
• A Novel CMOS Structure with Polysilicon Source/Drain (PSD) Transistors by Self-Aligned Silicidation (Special Issue on Sub-Half Micron Si Device and Process Technologies)
• Clarification of Nitridation Effect on Oxide Formation Methods
• W-Polymetal Gate with Low W/Poly-Si Interface Resistance for High-Speed/High-Density Embedded Memory
• Impact of Nitrogen Implantation on Highly Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors (MOSFETs) with Lightly Doped Drain Structure
• Substrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiency

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