Design of the Dataflow Single-Chip Processor EMC-R

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概要

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• This paper presents the design of the dataflow single-chip processor EMC-R, from the viewpoint of advanced dataflow schemes and their implementations. The EMC-R is a component chip of a highly parallel (with more than a thousand processors) dataflow machine, the EM-4. The distinctive features of the chip are: (1) a refined dataflow model called a strongly connected arc model, (2) two simple and fast synchronization mechanisms, (3)a versatile pipeline design, (4) a RISC-based architecture, (5) a packet-switching unit design with extra facilities and (6) a maintenance architecture for monitoring the system. After these features have been examined, the configuration architecture of the EMC-R that makes them possible is shown. There are six units on the chip: a switching unit, an input buffer unit, a fetch and matching unit, an execution unit, a memory control unit and a maintenance controller. The EMC-R is a CMOS gate array chip containing 45, 788 gates and using 255 signal pins. It is mounted on a PGA ceramic package. The EM-4 prototype system with 80 EMC-Rs is available now. Its hardware system was completed in April 1990. The purposes of the prototype are (1) to evaluate several architectural aspects by measuring dynamic characteristics of practical programs, (2) to confirm the architectural design, and (3) to provide an environment for software development.

• 一般社団法人情報処理学会の論文
• 1990-08-25

著者

• Yamaguchi Y

  Tohoku Univ. Sendai

• KODAMA Yuetsu

  Electrotechnical Laboratory

• SAKAI Shuichi

  Electrotechnical Laboratory

• YAMAGUCHI Yoshinori

  Electrotechnical Laboratory

• HIRAKI KEI

  Electrotechnical Laboratory

• YUBA TOSHITSUGU

  Electrotechnical Laboratory

• Yamaguchi Y

  Electrotechnical Laboratory

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