2-Dimensional Simulation of FN Current Suppression Including Phonon Assisted Tunneling Model in Silicon Dioxide
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概要
- 論文の詳細を見る
A gate oxide excess current model is described based on the phonon-assisted tunneling process of electrons into neutral traps. The influence on local electric field of charge of electrons trapped by neutral traps in gate oxide is simulated using a two-dimensional device simulator into which the new model is incorporated. FN current is suppressed with an increase in the neutral trap density to over 10~19 cm~-3. The calculated results reflect the endurance characteristics of flash memories in which erase/write operation speed depends on FN current.
- 社団法人電子情報通信学会の論文
- 1999-06-25
著者
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NISHIMURA Tadashi
the ULSI Development Center, Mitsubishi Electric Corporation
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Nishimura Tadashi
The Ulsi Development Center Mitsubishi Electric Corporation
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Nishimura Tadashi
Ulsi Research And Development Center Mitsubishi Electric Corporation
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Ishikawa K
Mitsubishi Electric Corp. Itami‐shi Jpn
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EIKYU Katsumi
the ULSI Development Center, Mitsubishi Electric Corporation
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SAKAKIBARA Kiyohiko
the System LSI Division, Mitsubishi Electric Corporation
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ISHIKAWA Kiyoshi
the ULSI Development Center, Mitsubishi Electric Corporation
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Eikyu K
Mitsubishi Electric Corp. Hyogo Jpn
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Ishikawa K
Renesas Technol. Corp. Hyogo Jpn
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Sakakibara Kiyohiko
The System Lsi Division Mitsubishi Electric Corporation
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