Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits

スポンサーリンク

概要

• 論文の詳細を見る
• 社団法人応用物理学会の論文
• 2002-03-15

著者

• Lee Joo-hyoung

  Memory R&d Division Hynix Semiconductor Co.

• Lee Jong-ho

  School Of Electrical Engineering Wonkwang University

• Lee J‐h

  Lg Electronics Inst. Technol. Seoul Kor

• Park Young

  School Of Mechanical Engineering Yonsei University

• Lee J‐h

  Wonkwang Univ. Chonpuk Kor

• Min Hong

  School Of Electrical Engineering And Computer Science And Isrc Seoul National University

• Min Hong

  School Of Electrical Engineering & Isrc Seoul National University

• Park Young

  School Of Electrical Engineering And Computer Science And Inter-university Of Semiconductor Research

• Park Young

  School Of Electrical Engineering & Isrc Seoul National University

• Park Young

  Department Of Electronics Engineering And Inter University Semiconductor Research Center Seoul Natio

• Lee Hyeokjae

  School Of Electrical Engineering Kookmin University

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

• Park Young

  School Of Electrical And Computer Engineering Sungkyunkwan University

• Lee Ju-Hyeon

  School of Electrical Engineering, Wonkwang University

• Lee Jong-Ho

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

関連論文

• Characterization of the Co-Silicide Penetration Depth into the Junction Area for 0.15 and Sub-0.15 Micron CMOS Technology
• The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability
• The Method to Optimize Gate Oxide Integrity, Hot Carrier Effect and Electro-Static Discharge without Sacrificing the Performance in Sub-Quarter Micron Dual Gate Oxide Process
• Analytical Model of Human Body Model Electrostatic Discharge Current Distribution and Novel Electrostatic Discharge Protection Structure
• A Novel Thin Gate-Oxide-Thickness Measurement Method by LDD (Lightly-Doped-Drain)-NMOS (N-Channel Metal-Oxide-Semiconductor) Transistors
• Characterization of the Co-Silicide Penetration Depth into the Junction Area
• Self-Induced Transparency in Samarium Atomic Vapor under Condition of High Temperature and High Density
• Effect of Microwave Pulse on the Optical Properties of Hydrogenated Amorphous Silicon Thin Films Deposited by Electron Cyclotron Resonance Plasma
• 2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
• Device Design Consideration for 50nm Dynamic Random Access Memory Using Bulk FinFET
• Laser Graphic Video Display using Silicon Scanning Mirrors with Vertical Comb Fingers
• Characterization of Silicon Scanning Mirror for Laser Display
• Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
• Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
• Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
• ORS-08 ROBUST H_∞ LOOP-SHAPING DESIGN FOR AN OPTICAL DISK DRIVE SYSTEM
• Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
• Origin of Abnormal Grain Growth in Tungsten Bronze Structured Ferroelectric Sr_xBa_Nb_2O_6 Ceramics
• Site Occupancy and Dielectric Characteristics of Strontium Barium Niobate Ceramics : Sr/Ba Ratio Dependence
• Ring Dark Solitary Waves on a Gaussian Background Beam
• Noise Performance of Pseudomorphic AlGaAs/InGaAs/GaAs High Electron Mobility Transistors with Wide Head T-Shaped Gate Recessed by Electron Cyclotron Resonance Plasma Etching
• Extremely Low Noise 0.15μm T-Gate AlGaAs/InGaAs Pseudomorphic HEMTs
• Low Noise Characteristics of 0.2μm Al_Ga_As/In_Ga_As/GaAs Pseudomorphic HEMTs with Wide Head T-Shaped Multifinger Gate
• Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer
• Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
• High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
• Pt and RuO_2 Bottom Electrode Effects on Pb(Zr,Ti)O_3 Memory Capacitors
• Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits
• Anomalous Noise Degradation Caused by Device Size Effects in SOI MOSFETs
• AC Floating Body Effects and 1/f Noise Characteristics of Dual Body SOI Structure for Analog-Digital Mixed Mode Circuit
• Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
• [Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• [Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• A New Charge Pumping Device
• A New Charge Pumping Device
• An Analysis of the Field Dependence of Interface Trap Generation under Negative Bias Temperature Instability Stress using Wentzel--Kramers--Brillouin with Density Gradient Method
• Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
• Inductively Coupled Plasma Etching of Chemical-Vapor-Deposited Amorphous Carbon in N2/O2/Ar Chemistries
• Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors
• Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor
• Flash Memory Device with ‘I’ Shape Floating Gate for Sub-70 nm NAND Flash Memory
• Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors
• Under Field Oxide Dopant Enhancement (UFDE) for CMOS and BiCMOS Technology
• DISTURBANCE MEASUREMENT OF OPTICAL DISC AND SERVO LOOP DESIGN RELATED TO ITS RESULT
• Spatial Distribution of Oxide Traps in Stressed Flash Memory
• Device design of SONOS flash memory cell with saddle type channel structure (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Device design of SONOS flash memory cell with saddle type channel structure (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
• Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function
• Effects of Body Doping in a NAND Flash String without Source/Drain
• NAND Flash Memory String with Localized Buried Oxide Layer
• Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions
• Investigation of the Low-Frequency Noise Behavior and Its Correlation with the Subgap Density of States and Bias-Induced Instabilities in Amorphous InGaZnO Thin-Film Transistors with Various Oxygen Flow Rates
• Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
• Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering
• Enhancement of Temperature Sensitivity for Metal--Insulator--Semiconductor Temperature Sensors by Using Bi2Mg2/3Nb4/3O7 Film
• New Multiple-Times Programmable CMOS ROM Cell
• Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
• Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET
• Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias
• Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions
• Design Technique for Ramped Gate Soft-Programming in Over-Erased NOR Type Flash EEPROM Cells
• Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure
• Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer
• Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure
• Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory
• Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors
• Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory
• High Speed, Low Power Programming in 0.17μm Channel Length NOR-type Floating Gate Flash Memory Cell Free of Drain Turn-On Effects
• Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory (Special Issue : Microprocesses and Nanotechnology)
• Two-Bit/Cell Characteristics of Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Devices with Recessed Channel Structure
• Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel
• Spatial Distribution of Oxide Traps in Stressed Flash Memory

もっと見る 閉じる

スポンサーリンク