Lee Jong-Ho | School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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著作論文

2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits
AC Floating Body Effects and 1/f Noise Characteristics of Dual Body SOI Structure for Analog-Digital Mixed Mode Circuit
[Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
[Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors
Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor
Flash Memory Device with ‘I’ Shape Floating Gate for Sub-70 nm NAND Flash Memory
Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors
Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function
Effects of Body Doping in a NAND Flash String without Source/Drain
Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions
Investigation of the Low-Frequency Noise Behavior and Its Correlation with the Subgap Density of States and Bias-Induced Instabilities in Amorphous InGaZnO Thin-Film Transistors with Various Oxygen Flow Rates
Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
Enhancement of Temperature Sensitivity for Metal--Insulator--Semiconductor Temperature Sensors by Using Bi2Mg2/3Nb4/3O7 Film
Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET
Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions
Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure
Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory
Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory (Special Issue : Microprocesses and Nanotechnology)

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