Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure

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概要

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• We characterized length effect of the spacer-type storage node in 2-bit/cell silicon–oxide–nitride–oxide–silicon (SONOS) flash memory device with recessed channel structure for 50 nm non-volatile memory (NVM) technologies. A proposed memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region. Device which has the charge storage length of 40 nm shown better $\Delta V_{\text{th}}$ and $V_{\text{th}}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10$ nm below the source/drain junction. Especially, in case of given read bias for forward or reverse read, the sensing current was more stable with shorter length of the storage layer.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2007-10-15

著者

• Jung Han-a-reum

  School Of Eecs Kyungpook National University

• Han Kyoung-rok

  School Of Electrical Engineering And Computer Science Kyungpook National Univ.

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

• Han Kyoung-Rok

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea

• Jung Han-A-Reum

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea

• Lee Jong-Ho

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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