Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors

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For given gate lengths ($L_{\text{g}}\leq 40$ nm) and fin body widths ($W_{\text{fin}}\leq 30$ nm), p+/n+ and n+/p+/n+ gate bulk fin field effect transistors (FinFETs) with a source/drain to gate underlap were designed to overcome the challenges in a sub-40 nm technology node. Their characteristics were compared with those of p+ gate bulk FinFETs through three-dimensional device simulation. We concentrated on device characteristics, such as on state current ($I_{\text{on}}$), off state current ($I_{\text{off}}$), subthreshold swing (SS), and drain-induced barrier lowering (DIBL), by controlling the overlap length of the source/drain-to-gate electrode and fin body width ($W_{\text{fin}}$). We also investigated the characteristics of p+/n+ and n+/p+/n+ gate bulk FinFETs with various n+ gate lengths ($L_{\text{s}}$’s).
2009-03-25