Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors

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概要

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• We present a comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors (MOSFETs) and p+/n+ gate bulk fin field effect transistors (FinFETs) that have been proposed for sub-40 nm dynamic random access memory (DRAM) applications. The p+/n+ gate structure consists of polycrystalline silicon (poly-Si) with two different work functions, so that the gate-induced-drain-leakage (GIDL) current of both devices can markedly be reduced. Device characteristics were carefully investigated in terms of on/off current ratio ($I_{\text{on}}/I_{\text{off}}$) and subthreshold swing (SS) by changing fin body width ($W_{\text{b}}$), and we analyzed drain current–gate voltage ($I$–$V$) characteristics and electric field profiles of a 40 nm device by controlling n+ gate length ($L_{\text{s}}$). Finally, electrical characteristics with respect to gate length ($L_{\text{g}}$) are also compared.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2008-07-25

著者

• Park Ki-heung

  School Of Eecs Kyungpook National University

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

関連論文

• 2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
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• Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
• Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
• Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
• Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits
• AC Floating Body Effects and 1/f Noise Characteristics of Dual Body SOI Structure for Analog-Digital Mixed Mode Circuit
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• [Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
• Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors
• Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor
• Flash Memory Device with ‘I’ Shape Floating Gate for Sub-70 nm NAND Flash Memory
• Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors
• Device design of SONOS flash memory cell with saddle type channel structure (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Device design of SONOS flash memory cell with saddle type channel structure (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
• Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function
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• NAND Flash Memory String with Localized Buried Oxide Layer
• Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions
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• Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering
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• Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure
• Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory
• Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors
• Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory
• Two-Bit/Cell Characteristics of Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Devices with Recessed Channel Structure
• Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel

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