Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

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概要

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• Device design using body-tied fin field effect transistor (bulk FinFET) was considered for the application to 50 nm DRAM technology. We concentrated on the device characteristics such as threshold voltage ($V_{\text{th}}$), off-state leakage current ($I_{\text{off}}$), subthreshold swing (S.S), and drain induced barrier lowering (DIBL) by controlling lightly doped drain (LDD) profile of the bulk FinFET. Bulk FinFETs with 0 to 3 nm non-overlap between source/drain (S/D) to gate electrode show lower $I_{\text{off}}$, S.S, and DIBL than those with an overlap while maintaining reasonable threshold voltage. We also compared characteristics of the triple gate bulk FinFET with those of the double gate bulk FinFET. Finally, electrical characteristics with LDD doping profile, S/D to gate overlap length, top gate oxide thickness, body doping concentration, fin top doping concentration, and doping profile from the edge to the center of the fin body are also compared.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2005-04-15

著者

• Choi Byung-kil

  School Of Electrical Engineering And Computer Science Kyungpook National Univ.

• Han Kyoung-rok

  School Of Electrical Engineering And Computer Science Kyungpook National Univ.

• Chung In-young

  Department Of Electronic Engineering Gyeongsang National University

• Yoon Euijoon

  School Of Electronic And Electrical Engineering Kyungpook National University

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

• Park Tai-su

  School Of Material Science Engineering Seoul National University

• Choi Byung-Kil

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Korea (ROK)

• Lee Jong-Ho

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Korea (ROK)

• Han Kyoung-Rok

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Korea (ROK)

• Chung In-Young

  Department of Electronic Engineering, Gyeongsang National University, Jinju, Korea (ROK)

• Yoon Euijoon

  School of Materials Science and Engineering, Seoul National University, Seoul, Korea (ROK)

• Park Tai-su

  School of Materials Science and Engineering, Seoul National University, Seoul, Korea (ROK)

• Lee Jong-Ho

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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