New Multiple-Times Programmable CMOS ROM Cell

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概要

• 論文の詳細を見る

• New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

• 2012-06-01

著者

• Chung In-young

  Department Of Electronic Engineering Gyeongsang National University

• Jeong Seong

  Department Of Chemical Engineering Sungkyunkwan University

• Park Young

  School Of Electrical And Computer Engineering Sungkyunkwan University

• CHUNG In-Young

  Department of Electronics and Communications Engineering, Kwangwoon University

• SEO Sung

  School of Electrical Engineering, Seoul National University

• Cha Seon-Yong

  R&D Division, Hynix Semiconductor Inc., San 136-1 Ami-ri, Bubal-eub, Ichon, Kyoungki-do 467-701, Korea

• CHA Seon-Yong

  R&D Division, Hynix Semiconductor Inc.

• LEE Myungjin

  R&D Division, Hynix Semiconductor Inc.

• JANG Taesu

  R&D Division, Hynix Semiconductor Inc.

• Jeong Seong

  Department of Ceramic Engineering, Yonsei University, Seoul 120-749, Korea

• PARK Young

  School of Electrical Engineering, Seoul National University

• JANG Taesu

  R&D Division, Hynix Semiconductor Inc.

• JEONG Seong

  Department of Electronics and Communications Engineering, Kwangwoon University

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