Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering

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概要

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• Threshold voltage ($V_{\text{th}}$) modeling of the double/triple-gate bulk fin field-effect transistors (FinFETs) was performed by considering the potential lowering at the surface of fin body at $V_{\text{GS}}=V_{\text{th}}$ condition. With decreasing gate length and/or fin width, the surface band-bending ($2\psi_{\text{B}}$) at $V_{\text{GS}}=V_{\text{th}}$ in fully depleted bulk FinFETs decreases since actual surface potential decreases at the $V_{\text{th}}$ condition. Based on the $2\psi_{\text{B}}$ correction, charge-sharing length ($x_{\text{h}}$) and corner factor ($\alpha_{\text{c}}$) were newly extracted. The $V_{\text{th}}$ behaviors of bulk FinFETs were modeled based on the surface potential lowering, three-dimensional (3-D) charge-sharing, narrow-width effect, and corner factor. The $V_{\text{th}}$ model predicted well the $V_{\text{th}}$ behavior with fin body width, body doping concentration, gate length, gate height, and corner shape of the fin body. Our compact models predicted accurately $V_{\text{th}}$ of the devices with the gate length up to 20 nm and the fin body width up to 5 nm.

• 2008-05-25

著者

• Choi Byung-kil

  School Of Electrical Engineering And Computer Science Kyungpook National Univ.

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

• Choi Byung-Kil

  School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu 702-701, Korea

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