Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
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概要
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We proposed p^+/n^+ gate bulk FinFETs that has a locally seperate channel (LSC) and non-overlapped S/D to gate structure, and shown improved scalability. The key device characteristics were investigated by using extensive simulations, and the speed characteristics were studied with a non-overlap distance. For the non-overlap LSC FinFET structure, device characteristics with gate length (L_g), channel fin width (W_<cfin>) and non-overlap length (L_<no>) were carefully investigated in terms of the drain induce barrier lowering (DIBL), off-state leakage current (I_<off>), subthreshold swing (SS), and threshold voltage (V_<th>). The non-overlap LSC FinFET structure showed improving DIBL and SS as L_<no> increases. These results show that the non-overlapped S/D to gate structure is useful in suppressing the SCE by increasing effective channel length. We also obtained much lower I_<off> and wider process margin compared to those of overlap LSC structure. The devices with an L_<no> of longer than 0nm give lower I_<off> by 〜100 times than that of the device with an L_<no> of-5nm. As a result, we could achieve optimum non-overlap length about 〜5nm. The proposed structure had good I_<on>/I_<off> and DIBL characteristics compared to those of overlapped structure.
- 2008-07-02
著者
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Lee Jong-ho
School Of Electrical Engineering Wonkwang University
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Lee Jong-ho
School Of Electronic Engineering Daegu University Jillyang
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Jung Han-a-reum
School Of Eecs Kyungpook National University
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PARK Ki-Heung
School of Electrical Engineering and Computer Science, Kyungpook National Univ.
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Park Ki-heung
School Of Eecs Kyungpook National University
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Kwon Hyuck-in
School Of Eecs Kyungpook National University
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Lee Jong-ho
School Of Eecs Engineering Kyungpook National University
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Lee Jong-Ho
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
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