Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

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概要

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• Inversion charge ($Q_{\text{i}}$) and oxide capacitance ($C_{\text{ox}}'$) of undoped (or lightly doped) or doped double-gate (DG) and surrounding-gate (SG) metal–oxide–semiconductor field-effect transistors (MOSFETs) with long channel were analytically modeled by considering inversion-layer capacitance ($C_{\text{i}}$) in linear region. The $Q_{\text{i}}$ model of DG and SG MOSFETs was derived with a closed-form as a function of gate bias ($V_{\text{GS}}$), threshold voltage ($V_{\text{th}}$), and body structure factor ($n$) using one-dimensional (1D) Poisson’s equation considering the mobile carrier. The $n$ which reflects silicon body structure effect is 1 for DG MOSFETs and less than 1 for SG MOSFETs irrespective of channel doping ($N_{\text{b}}$). From the derived $Q_{\text{i}}$ model considering the $C_{\text{i}}$ effect, the $C_{\text{ox}}'$ was modeled and applied to the $I_{\text{D}}$–$V_{\text{GS}}$ model of undoped or doped DG and SG MOSFETs in linear region. The compact current model using our proposed $C_{\text{ox}}'$ predicted more accurately the on-current behavior than that with the oxide capacitance ($C_{\text{ox}}$) in linear region.

• 2010-10-25

著者

• Kwon Hyuck-in

  School Of Eecs Kyungpook National University

• Choi Byung-Kil

  Memory R&D Division, Hynix Semiconductor Inc., Ichon, Gyeonggi-do 467-701, Korea

• Jeong Min-Kyu

  ISRC and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea

• Lee Jong-Ho

  ISRC and School of Electrical Engineering, Seoul National University, Seoul 151-742, Korea

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