Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias

概要

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The threshold voltage ($V_{\text{th}}$) was modeled in a simple closed form by considering drain bias ($V_{\text{DS}}$) for fully depleted (FD) symmetric double-gate (DG) n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with doped short channels. The $V_{\text{th}}$ model using only two parameters ($D_{\text{G}}$ and $D_{\text{D}}$) is based on $V_{\text{th0}}$ ($V_{\text{th}}$ at low $V_{\text{DS}}$), and derived from the diffusion current of doped DG MOSFETs that was modeled using surface potential ($\Phi_{\text{s}}$). $D_{\text{G}}$ and $D_{\text{D}}$ are parameters for considering the gate bias ($V_{\text{GS}}$) dependence and $V_{\text{DS}}$ dependence, respectively, in the diffusion current model. Our compact $V_{\text{th}}$ model predicted the threshold voltage behavior by considering $V_{\text{DS}}$ more accurately than the constant current (CC) method down to a channel length ($L$) of 30 nm.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2009-05-25