[Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)

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概要

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• We review briefly double-gate CMOS devices reported and propose a new body-tied FinFET which is built on bulk Si wafers instead of SOI wafers. Device characteristics and internal physics such as potential of the body-tied FinFETs are shown. Scaling-down characteristics of the proposed devices were studied in detail by comparing those of SOI FinFETs. The channel doping is selectively changed in the vertical position of the fin body and its effects are shown in terms of V_T and I_<off>. We fabricated 120 nm body-tied FinFETs and shown key process steps and electrical results. The proposed MOSFET shows lower Drain Induced Barrier Lowering (DIBL) and much smaller body bias effect than planar type DRAM cell transistors.

• 社団法人電子情報通信学会の論文
• 2003-06-23

著者

• YOON Euijoon

  School of Materials Science and Engineering, Seoul National University

• Lee J‐h

  School Of Electrical Engineering And Computer Science Kyungpook National Univ.

• Lee Jong-ho

  School Of Electrical Engineering Wonkwang University

• PARK Tai-su

  School of Materials Science and Engineering, Seoul National University

• Park Tai-su

  School Of Materials Science And Engineering Seoul National University

• Yoon Euijoon

  School Of Electronic And Electrical Engineering Kyungpook National University

• Lee Jong-ho

  School Of Eecs Engineering Kyungpook National University

• Park Tai-su

  School Of Material Science Engineering Seoul National University

• Lee Jong-Ho

  School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

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