Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
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概要
- 論文の詳細を見る
A new MOS device (called modified Saddle MOSFET) with recess channel and side-gate was proposed, and key features of the device were characterized through 3-dimensional device simulation for the first time. The Saddle MOSFET structure was modified to have smaller GIDL and lower source/drain to gate overlap capacitance. It was about 21% lower gate capacitance and lower I_<off> by two orders of magnitude than Saddle device while keeping nearly same I_<on> current. In addition, the proposed MOSFETs shown less threshold voltage (V_<th>) sensitivity with the comer shape than conventional recess channel devices, and shown lower gate delay time (CV/I) by〜30% than the conventional devices while keeping nearly the same I_<off>.
- 社団法人電子情報通信学会の論文
- 2006-06-26
著者
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Park Ki-heung
School Of Eecs Kyungpook National University
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Lee Jong-ho
School Of Eecs Engineering Kyungpook National University
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Lee Jong-Ho
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
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