Enhancement of Temperature Sensitivity for Metal--Insulator--Semiconductor Temperature Sensors by Using Bi2Mg2/3Nb4/3O7 Film
スポンサーリンク
概要
- 論文の詳細を見る
Metal--insulator--semiconductor (MIS) type temperature sensors with Bi2Mg2/3Nb4/3O7 (BMNO) film are introduced to improve temperature detecting ability. The current gain of presented sensor is nearly 180 within 7--77 °C which is more than the double amount of current gain in previous work. Dielectric thickness dependency of sensor is also decreased comparing with previous sensor. Temperature detecting mechanisms were analyzed by current and temperature relationship. It was also shown that these sensors were reliable through the temperature cycling test.
- 2012-08-25
著者
-
Lee Jae-min
Department Of Electronic Materials Engineering Kwangwoon University
-
Cho Il
Department Of Biotechnology Chung-ang University
-
Lee Jong-ho
School Of Eecs Engineering Kyungpook National University
-
Cho In-Tak
School of Electrical Engineering and Computer Science, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu 702-701, Korea
-
Yoon Soon-Gil
School of Nano Science and Technology, Chungnam National University, Daeduk Science Town, Daejeon 305-764, Korea
-
Yoon Soon-Gil
School of Nano Science and Technology, Chungnam National University, Daejon 305-764, Republic of Korea
-
Lee Jae-Min
Department of Electronic Engineering, Myongji University, Yongin, Gyeonggi 449-728, Republic of Korea
-
Lee Jong-Ho
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
関連論文
- 2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
- Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
- Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
- Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
- Characterization of Lactobacillus spp. isolated from the feces of breast-feeding piglets(MICROBIAL PHYSIOLOGY AND BIOTECHNOLOGY)
- Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits
- AC Floating Body Effects and 1/f Noise Characteristics of Dual Body SOI Structure for Analog-Digital Mixed Mode Circuit
- [Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- [Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
- Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors
- Electrical Property and Long-Term Stability of Transparent Capacitors Using Multi-Layer Transparent Conducting Oxide Electrodes
- Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor
- Full-Swing InGaZnO Thin Film Transistor Inverter with Depletion Load
- Flash Memory Device with ‘I’ Shape Floating Gate for Sub-70 nm NAND Flash Memory
- Device Design of p+/n+ and n+/p+/n+ Gate Bulk Fin Field Effect Transistors with Source/Drain to Gate Underlap for Sub-40 nm Dynamic Random Access Memory Cell Transistors
- Device design of SONOS flash memory cell with saddle type channel structure (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Device design of SONOS flash memory cell with saddle type channel structure (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
- Electrical Switching Studies of Amorphous Ge1Se1Te2 Thin Film for a High-Performance Nonvolatile Phase-Change Memory
- Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function
- Effects of Body Doping in a NAND Flash String without Source/Drain
- NAND Flash Memory String with Localized Buried Oxide Layer
- Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions
- Investigation of the Low-Frequency Noise Behavior and Its Correlation with the Subgap Density of States and Bias-Induced Instabilities in Amorphous InGaZnO Thin-Film Transistors with Various Oxygen Flow Rates
- Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
- Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering
- Enhancement of Temperature Sensitivity for Metal--Insulator--Semiconductor Temperature Sensors by Using Bi2Mg2/3Nb4/3O7 Film
- Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
- Modeling of Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory
- Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET
- Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias
- Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions
- Band-to-Band Hot-hole Erase Characteristics of 2-Bit/cell NOR-type Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Cell with Spacer-type Storage Node on Recessed Channel Structure
- Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer
- Length Effect of Spacer-Type Storage Node in High-Density 2-bit/Cell Silicon–Oxide–Nitride–Oxide–Silicon NOR Flash Cell Based on Recessed Channel Structure
- Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory
- Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors
- Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory
- Modeling of Triangular Sacrificial Layer Residue Effect in Nano-Electro-Mechanical Nonvolatile Memory
- Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory (Special Issue : Microprocesses and Nanotechnology)
- Two-Bit/Cell Characteristics of Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory Devices with Recessed Channel Structure
- Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel