Lee Jong-ho | School Of Electrical Engineering Wonkwang University

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概要

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著作論文

2-bit/cell Characteristics of High-Density and High-Performance SONOS Flash Memory Cell with Recessed Channel Structure
Device Design Consideration for 50nm Dynamic Random Access Memory Using Bulk FinFET
Threshold Voltage Behavior of Body-Tied FinFET (OMEGA MOSFET) with Respect to Ion Implantation Conditions
Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
Characteristics of Locally-Separated Channel FinFETs with Non-Overlapped Source/Drain to Gate for Sub-50nm DRAM Cell Transistors(Session2: Silicon Devices I)
Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer
Time-Varying Body Instability and Low-Frequency Noise Characteristics of Mini-Field-Dual-Body Silicon-on-Insulator Structure for Analog-Digital Mixed-Mode Circuits
AC Floating Body Effects and 1/f Noise Characteristics of Dual Body SOI Structure for Analog-Digital Mixed Mode Circuit
Isotropic/Anisotropic Selective Epitaxial Growth of Si on Local Oxidation of Silicon (LOCOS) Patterned Si (100) Substrate by Cold Wall Ultrahigh Vacuum Chemical Vapor Deposition (UHV-CVD)
[Invited]Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
[Invited] Double-Gate MOSFETs for Nano CMOS Technology : Body-tied Double-Gate MOSFETs (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
Modified Saddle MOSFETs for Sub-50nm DRAM Technology(Session 1 Silicon Devices I,AWAD2006)
Gate Workfunction Engineering of Bulk FinFETs for Sub-50nm DRAM Cell Transistors

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