Park Byung-Gook | School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea

スポンサーリンク

概要

関連著者

もっと見る

著作論文

Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
A New 1T DRAM Cell : Cone Type 1T DRAM Cell
Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
Monte Carlo Simulation of Single-Electron Nanocrystal Memories
Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory
Characterization of Sensitivity and Resolution of Silicon Resistive Probe
Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory
Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory (Special Issue : Microprocesses and Nanotechnology)

もっと見る

スポンサーリンク