Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
スポンサーリンク
概要
- 論文の詳細を見る
- 2009-07-25
著者
-
Park Byung‐gook
School Of Electrical Engineering Seoul National University
-
Park Byung-gook
School Of Electrical Engineering Seoul National University
-
Park Byung‐gook
Seoul National Univ. Seoul Kor
-
Lee J
School Of Electrical Engineering Seoul National University
-
KANG Daewoong
School of Electrical Engineering, Seoul National University
-
YANG Seungwon
School of Electrical Engineering, Seoul National University
-
LEE Jong
School of Electrical Engineering, Seoul National University
-
SHIN Hyungcheol
School of Electrical Engineering, Seoul National University
-
Lee J
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
Lee Jong
School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.
-
Lee Joung-eob
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
Shin Hyungcheol
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
-
Shin Hyungcheol
School Of Electrical Engineering And Computer Science Seoul National University
-
Lee Jong
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
-
Kang Daewoong
School Of Electrical Engineering Seoul National University
-
Yang Seungwon
School Of Electrical Engineering Seoul National University
-
Park Byung-gook
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
-
Lee Jong
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
-
Lee Jong
Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni
-
Park Byung-gook
School Of Electrical Engineering And Computer Sciences And The Inter-university Semiconductor Resear
-
Park Byung-gook
Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U
-
Yang Seungwon
School of Electrical Engineering and Computer Science, Seoul National University, #059, San 56-1, Sillim-dong, Kwanak-gu, Seoul 151-742, Korea
-
Shin Hyungcheol
School of Electrical Eng.
-
Park Byung-Gook
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
関連論文
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- 2P4-3 横振動により接合された高延性ENIGめっき電極の評価(ポスターセッション)
- Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
- Nanoscale Multi-Line Patterning Using Sidewall Structure
- Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
- Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire