4-bit FinFET SONOS flash memory: Optimization of structure and 3D numerical simulation (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
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概要
- 論文の詳細を見る
We study the 4-bit FinFET SONOS memory which is based on double gate MOSFETs. It is operated by channel hot electron injection (CHEI)/hot hole injection (HHI) as program/erase (P/E) mechanisms. The array of the device is based on NOR-type structure. In this paper, an improved array structure of the device is proposed. The program characteristics associated with junction depth are further investigated using 3D SILVACO ATLAS simulation.
- 社団法人電子情報通信学会の論文
- 2007-06-18
著者
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Park Byung-gook
School Of Electrical Engineering Seoul National University
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Yun Jang‐gn
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Kim Yoon
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
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Kim Yoon
School Of Advanced Technology And Liaison Research Institute Kyung Hee University
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YUN Jang-Gn
School of Electrical Engineering and Computer Science, Seoul National University
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Yun Jang
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
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Yur Jang-Gn
School of Electrical Engineering, Seoul National University
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Kim Yoon
School Of Electrical Engineering Seoul National University
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Yur Jang-gn
School Of Electrical Engineering Seoul National University
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Park Byung-gook
School Of Electrical Engineering And Computer Sciences And The Inter-university Semiconductor Resear
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Park Byung-Gook
School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Korea
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Park Byung-Gook
School of Electrical Engineering & Inter-University Semiconductor Research Center (ISRC), Seoul National University, Shilim-Dong, Kwanak-Gu, Seoul 151-742, Republic of Korea
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Park Byung-Gook
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
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