Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs

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概要

• 論文の詳細を見る
• 2007-09-19

著者

• Park Byung‐gook

  School Of Electrical Engineering Seoul National University

• Park Byung-gook

  School Of Electrical Engineering Seoul National University

• Lee J

  School Of Electrical Engineering Seoul National University

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Lee Joung-eob

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• KIM Jinjoo

  School of Electrical Engineering, Seoul National University

• Kim Jinjoo

  School Of Electrical Engineering Seoul National University

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• KIM Junsoo

  Nano Systems Institutes, and School of EE, Seoul National University

• LEE Jaehong

  Nano Systems Institutes, and School of EE, Seoul National University

• YUN Yeonam

  Nano Systems Institutes, and School of EE, Seoul National University

• PARK Byung-Gook

  Nano Systems Institutes, and School of EE, Seoul National University

• LEE Jong

  Nano Systems Institutes, and School of EE, Seoul National University

• SHIN Hyungcheol

  Nano Systems Institutes, and School of EE, Seoul National University

• Yun Yeonam

  Nano Systems Institutes And School Of Ee Seoul National University

• Lee Jong

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Lee Jong

  Inter-university Semiconductor Research Center School Of Electrical Engineering Seoul Nat'l Uni

関連論文

• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
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• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Nanoscale Multi-Line Patterning Using Sidewall Structure
• Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
• Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
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• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
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