RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))

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概要

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• For the first time, three-dimensional device simulation of FinFETs to analyze RF linearity is reported. Device optimization was performed in order to suppress the short-channel effect (SCE) by reducing the sub-threshold swing and drain induced barrier lowering (DIBL). The RF linearity characteristics of FinFETs including triple gate and double gate (DG) structures were investigated. Linearity performance as a function of body thickness, drain bias, gate length was investigated in optimizing the device. We observed that the linearity increases gradually as the gate length is scaled down. The down scaling of body thickness has a negative impact on linearity for FinFETs.

• 2005-06-21

著者

• Song Jae

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Kang Myounggon

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Kim Dong

  Inter-University Semiconductor Research Center (ISRC), and School of Electrical Engineering, Seoul N

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc)

• Shin Hyungcheol

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Song Jae

  Inter-University Semiconductor Research Center (ISRC)

• Kang Myounggon

  Inter-University Semiconductor Research Center (ISRC)

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