Novel Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors with Self-Aligned Structure
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概要
- 論文の詳細を見る
We proposed a new self-aligned gate-all-around metal–oxide–semiconductor field effect transistor (MOSFET) with a wide source/drain region. The device was fabricated by using the concept of the self-aligned double-gate fin-type FETs (FinFETs) with additional processes. The minimum gate length and fin width were 35 and 20 nm, respectively. The gate oxide thickness was 2.4 nm. For the fabricated devices, we confirmed that drain induce barrier lowering (DIBL) and sub-threshold swing (SS) were properly suppressed in spite of the short channel length. We also performed a simulation-based analysis to explore the effects induced by oversized bottom gate in the proposed device structure. If the lateral source/drain doping gradient was not steep, the oversized bottom gate could lead to the enhancement of the gate controllability and the suppression of short channel effects. As a result, the intrinsic gate delay of the proposed devices was improved when the bottom gate was somewhat oversized.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-04-30
著者
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Choi Woo
Inter-university Semiconductor Research Center Seoul National University
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Lee Jong
Inter-univ. Semicon. Res. Center Seoul Nat. Univ.
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Kim Sang
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
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Kim Jong
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea
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Kim Jong
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Song Jae
Inter-University Semiconductor Research Center (ISRC)
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Park Byung-Gook
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
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Choi Woo
Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea
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Choi Woo
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea
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Lee Jong
Inter-University Semiconductor Research Center and School of Electrical Engineering, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Korea
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Park Byung-Gook
Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea
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