Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method

スポンサーリンク

概要

• 論文の詳細を見る
• 社団法人応用物理学会の論文
• 1994-05-15

著者

• LEE Jong

  Inter-University Semiconductor Research Center, Seoul National University

• Lee J

  School Of Electrical Engineering Seoul National University

• Kim Young

  Applied Physics Group Korea Institute Of Science And Technology

• Kim Y

  Sungkyukwan Univ. Kyunggi‐do Kor

• Lee Jae

  Korea Research Institute Of Chemical Technology

• KWON SANG

  Department of Internal Medicine and Institute of Lifelong Health, Yonsei University Wonju College of

• Chun Kuk

  Isrc Seoul National University

• Kwon Sang

  Dept. Of Electronics Eng. Kyungwon Univ.

• Lee Jong

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• KIM Yeo

  Inter-University Semiconductor Research Center, Seoul National University

• CHUN Kuk

  Inter-University Semiconductor Research Center, Seoul National University

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Kwon Sang

  Department Of Dermatology Hanyang University College Of Medicine

• Kwon Sang

  Department Of Chemistry Yeungnam University

関連論文

• T-3-2-1 Semi-Empirical Method for Real-time Vehicle Dynamic Simulation
• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Nanoscale Multi-Line Patterning Using Sidewall Structure
• Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
• Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
• Single Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
• Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Dual-gate single-electron transistor with silicon nano wire channel and surrounding side gates (Special issue: Solid state devices and materials)
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• 3P-12 超音波センサモジュールを用いたマルチポジショントラッキングシステムの設計(ポスターセッション)
• Ninety Degree Domains in RF-Sputtered BaTiO_3 Thin Films on Platinum Substrates
• (111) Twins in BaTiO_3 Thin Films Deposited by RF Magnetron Sputtering
• 2P-51 強力超音波によるイースト菌の細胞死(ポスターセッション)
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• 1Pb-44 小型電子部品の超音波接合とその評価(ポスターセッション)
• Full-swing pentacene organic inverter with long-channel driver and short-channel load
• A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
• Silicon Quantum Tunneling Devices - FIBTET and MOSET
• Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
• Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
• Channel Doping Engineering with Indium as an Alternative p-Type Dopant
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
• Novel Gate-All-Around MOSFETs with Self-Aligned Structure
• Multi-Functionality of Novel Structured Tunneling Devices
• Synchronous Mirror Delay for Multi-phase Locking
• Synchronous Mirror Delay for Multi-phase Locking
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs
• Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
• Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
• Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
• 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method
• As Preamorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p^+-n Junction
• Predicting Diametral Creep of the Pressure Tubes in CANDU Reactors Using Fuzzy Neural Networks
• Electronic Structure Simulation of Chromium Aluminum Oxynitride by Discrete Variational-Xa Method and X-Ray Photoelectron Spectroscopy
• Lateral Silicon Field-Emission Devices using EIectron Beam Lithography
• Silicon Nano-Crystal Memory with Tunneling Nitride
• Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
• Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
• Ultra Shallow p+n Junction Formation Using the Solid Phase Diffusion(SPD) through'a-Si/Thin Barrier Oxide' Layer
• Efficient Timing Verification of Latch-Synchronized Systems

もっと見る 閉じる

スポンサーリンク