Silicon Nano-Crystal Memory with Tunneling Nitride

スポンサーリンク

概要

• 論文の詳細を見る
• 1998-09-07

著者

• Lee J

  School Of Electrical Engineering Seoul National University

• Lee Jae

  Korea Research Institute Of Chemical Technology

• Shin Hyungcheol

  Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Science And Te

• Shin Hyungcheol

  Department Of Electrical Engineering Kaist

• Shin Hyungcheol

  Department Of Electrical Engineering And Computer Science Kaist

• Kim Ilgweon

  Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Science And Te

• LEE Jongho

  School of Electrical Engineering, Wonkwang University

• KIM Hyungsik

  LG Semicon Co., Ltd

• Lee Jongho

  School Of Electrical Eng. Wonkwang Univ.

• Kim Hyungsik

  Lg Semicon Co. Ltd

• Kim Ilgweon

  Department Of Electrical Engineering Kaist

• Lee Jongho

  School Of Electrical Engineering Wonkwang University

関連論文

• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
• Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Dual-gate single-electron transistor with silicon nano wire channel and surrounding side gates (Special issue: Solid state devices and materials)
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Channel Doping Engineering with Indium as an Alternative p-Type Dopant
• Synchronous Mirror Delay for Multi-phase Locking
• Synchronous Mirror Delay for Multi-phase Locking
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method
• As Preamorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p^+-n Junction
• Predicting Diametral Creep of the Pressure Tubes in CANDU Reactors Using Fuzzy Neural Networks
• Resonant Photoemission Spectroscopy and Theoretical Calculation of the Valence Band Structure in Chromium Aluminum Oxynitride
• Electronic Structure Simulation of Chromium Aluminum Oxynitride by Discrete Variational-Xa Method and X-Ray Photoelectron Spectroscopy
• Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects
• Lateral Silicon Field-Emission Devices using EIectron Beam Lithography
• Silicon Nano-Crystal Memory with Tunneling Nitride
• Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
• Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
• 40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication
• 40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication
• 40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication
• Remote Fabrication of DUPIC Fuel Pellets in a Hot Cell under Quality Assurance Program
• Gate-Induced Drain Leakage Currents in Metal Oxide Semiconductor Field Effect Transistors with High-κ Dielectric
• A New CMOS Passive Mixer with High Linearity
• ICONE11-36188 ALARA REVIEW OF THE MAINTENANCE AND REPAIR JOBS OF REPETITIVE HIGH RADIATION DOSE AT KORI UNIT 3 & 4
• A Nano-Structure Memory with Silicon on Insulator Edge Channel and a Nano Dot
• Development of Operator Action Time for SBLOCA during Plant Shutdown Operation in Power-uprated Kori 3 and 4
• Optimization for Setpoints of Steam Generator Water Level Control Systems in Power-uprated YGN 1 & 2 and Kori 3 & 4
• ED2000-80 / SDM2000-80 MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries
• Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects
• A New Physical RF Model of Junction Varactors
• Analysis of Random Telegraph Signal Noise in Dual and Single Oxide Device and Its Application to Complementary Metal Oxide Semiconductor Image Sensor Readout Circuit

もっと見る 閉じる

スポンサーリンク