40nm Electron Beam Patterning by Optimization of Digitizing Method and Post Exposure Bake and its Application to Silicon Nano-Fabrication
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概要
- 論文の詳細を見る
We experimented on the 40 nm paterning using E-beam lithography system. SAL601 negative E-beam resist was used for this experiment. In order to utilize the maximum ability of E-beam system, we reduced the PR thickness to 100 nm, and the field size to 200μm. Then, PEB(Post Expose Bake) time and temperature, which is one of the very important factors for nano-patterning, were reduced for minimum line width. In addition, digitizing was optimized for better results. Quantum wire and quantum dot which can be used for nano-scale memory device, such as single electron memory device, were fabricated using these developed lithography technique.
- 社団法人電子情報通信学会の論文
- 1999-07-22
著者
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Lee Kwyro
Department of Electrical Engineering, Korea Advanced Institute of Science and Technology
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Lee K
Korea Advanced Inst. Sci. And Technol. Kor
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Lee Kwyro
Department Of Eecs Korea Advanced Institute Of Science And Technology
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Shin Hyungcheol
Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Science And Te
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Shin Hyungcheol
Department Of Electrical Engineering And Computer Science Kaist
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HAN Sangyeon
Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and T
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Park Taejun
Department of Electrical Engineering, KAIST
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Kim Bonkee
Department of Electrical Engineering, KAIST
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Han Sangyeon
Department Of Electrical Engineering Kaist
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Han Sangyeon
Department Of Electrical Engineering And Computer Science Korea Advanced Institute Of Science And Te
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Kim Bonkee
Rf Products. System Lsi Business Semiconductor Samsung Electronics
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Park Taejun
Department Of Electrical Engineering Kaist
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Shin Hyungcheol
Department of Electrical Engineering, KAIST
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Lee Kwyro
Department of EE, Korea Advanced Institute of Science and Technology (KAIST)
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