Synchronous Mirror Delay for Multi-phase Locking

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概要

• 論文の詳細を見る

• A multi-phase synchronous circuit suited for DDR(double data rate) specification was designed using a SMD(synchronous mirror delay). The synchronizing error of the SMD was reduced under the delay time of unit delay stage by compensation characteristics of detecting circuit. By the compensating effect of the detecting circuit the synchronizing error of the SMD could be reduced to ±17ps for zero phase, which is smaller than the delay time of unit delay stage. For the multi-phase (90°in this paper) clock generation circuit including the SMD, the clock receiver, the clock driver and other additional circuits, the synchronizing error was less than ±40ps.

• 社団法人電子情報通信学会の論文
• 2002-06-24

著者

• Park Byung

  School Of Electrical Engineering Seoul National University

• Park Byung

  School Of Electrical Engeneering Seoul National University

• Lee J

  School Of Electrical Engineering Seoul National University

• LEE Jong

  School of Electrical Engineering, Seoul National University

• Lee Jong

  School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.

• Park B

  School Of Electrical Engineering Seoul National University

• Yoon Yong

  School Of Electrical Engineering Seoul National University

• Cho Uk

  Samsung Electronics Corp.

• Byun Hyun

  Samsung Electronics Corp.

• Lee Jae

  Korea Research Institute Of Chemical Technology

• Kim Nam

  Samsung Electronics Corp.

• Lee Jong

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

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