Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
スポンサーリンク
概要
- 論文の詳細を見る
- 2007-09-19
著者
-
LEE Jong
School of Electrical Engineering, Seoul National University
-
SHIN Hyungcheol
School of Electrical Engineering, Seoul National University
-
Lee Jong
School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.
-
Shin Hyungcheol
School Of Electrical Engineering And Computer Science Seoul National University
-
Shin Hyungcheol
School Of Electrical Engineering Seoul National University
-
Kang In
School Of Electrical Engineering Seoul National University
-
Lee Jong
School Of Electrical Engineering Seoul National University
-
YOON Yeonam
School of Electrical Engineering, Seoul National University
-
Yoon Yeonam
School Of Electrical Engineering Seoul National University
-
Shin Hyungcheol
School of Electrical Eng.
関連論文
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- 2P4-3 横振動により接合された高延性ENIGめっき電極の評価(ポスターセッション)
- Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
- Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Fuzzy Logic-Based Quantized Event Filter for RFID Data Processing
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- Control of the Microstructure of (Pb, La) TiO_3 Thin Films by Metal-Organic Chemical Vapor Deposition Using a Solid Delivery System for Ferroelectric Domain Memory
- Synchronous Mirror Delay for Multi-phase Locking
- Synchronous Mirror Delay for Multi-phase Locking
- Low cost CMOS LNA design using thin-metal CMOS process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low cost CMOS LNA design using thin-metal CMOS process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Simple Wide-Band Metal-Insulator-Metal (MIM) Capacitor Model for RF Applications and Effect of Substrate Grounded Shields
- Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Degradation and Recovery Phenomena of Thin Gate Oxide Films under Dynamic Negative-Bias Temperature Instability (NBTI) Stress (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Isolation of 151 Mutants that Have Developmental Defects from T-DNA Tagging
- Anomalous Noise Degradation Caused by Device Size Effects in SOI MOSFETs
- On the Bit Error Probability of 16DAPSK in a Frequency-Selective Fast Rayleigh Fading Channel with Cochannel Interference
- Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- Dependence of Contact Resistance on Substrate Doping and Impact of Mixed Ion Implantation
- Lateral Silicon Field-Emission Devices using EIectron Beam Lithography
- Monte Carlo Simulation of Single-Electron Nanocrystal Memories
- Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
- CARS temperature measurement in a Liquid Kerosene fueled Gas Turbine Combustor Sector Rigs(Measurement, Temperature)
- ED2000-80 / SDM2000-80 MOS Memory Using Si Nanocrystals Formed by Wet Etching of Poly-Silicon Along Grain Boundaries
- An advanced method for the determination of carboxyl methyl esterase activity using gas chromatography-chemical ionization-mass spectrometry
- CMOS low-noise amplifer with noise suppression technique from gate resistance (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- CMOS low-noise amplifer with noise suppression technique from gate resistance (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
- Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
- Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (Special Issue : Microprocesses and Nanotechnology)
- Extraction of T-Type Substrate Resistance Components for Radio-Frequency Metal--Oxide--Semiconductor Field-Effect Transistors Based on Two-Port S-Parameter Measurement
- Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics
- Performance of Gate-All-Around Tunneling Field-Effect Transistors Based on Si_Ge_x Layer
- Radio Frequency Performance of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors
- Simple Wide-Band Metal-Insulator-Metal (MIM) Capacitor Model for RF Applications and Effect of Substrate Grounded Shields
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- Monte Carlo Simulation of Single-Electron Nanocrystal Memories
- Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
- Novel Extraction Method for Source and Drain Series Resistances in Silicon Nanowire Metal--Oxide--Semiconductor Field-Effect-Transistors Based on Radio-Frequency Analysis
- Simultaneous Extraction of Locations and Energies of Two Independent Traps in Gate Oxide From Four-Level Random Telegraph Signal Noise
- Characterization of Sensitivity and Resolution of Silicon Resistive Probe
- Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation
- Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer
- Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel
- Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs