Rigorous Design and Analysis of Tunneling Field-Effect Transistor with Hetero-Gate-Dielectric and Tunneling-Boost n-Layer
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概要
- 論文の詳細を見る
A gate-all-around tunneling field-effect transistor (GAA TFET) with local high-k gate-dielectric and tunneling-boost n-layer based on silicon is demonstrated by two dimensional (2D) device simulation. Application of local high-k gate-dielectric and n-layer leads to reduce the tunneling barrier width between source and intrinsic channel regions. Thus, it can boost the on-current (Ion) characteristics of TFETs. For optimal design of the proposed device, a tendency of device characteristics has been analyzed in terms of the high-k dielectric length (Lhigh-k) for the fixed n-layer length (Ln-layer). The simulation results have been analyzed in terms of on- and off- current (Ion and Ioff), subthreshold swing (SS), and RF performances.
著者
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Kang In
School Of Electrical Engineering Seoul National University
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Seo Jae
School Of Computer And Electronics Engineering Keimyung University
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Lee Jae
School Of Computer Science And Engineering Seoul National University
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Lee Jung-Hee
School of Electrical Engineering & Computer Science, Kyungpook National University, Daegu 702-701, Korea
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SEO Jae
School of Electrical Engineering and Computer Science, Kyungpook National University
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PARK Yun
School of Electrical Engineering and Computer Science, Kyungpook National University
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