Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics
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概要
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In this paper, we propose a radio-frequency (RF) model and parameter extraction method for vertical junctionless silicon nanowire (VJL SNW) field-effect transistors (FETs) using three-dimensional (3D) device simulation. We introduce the substrate-related components such as the substrate resistance (R_{\text{sub}}) and drain-to-substrate capacitance (C_{\text{sub}}), and evaluate the RF performance such as f_{\text{t}}, f_{\text{max}}, gate input capacitance, and transport time delay. A quasi-static (QS) RF model has been used in simulation program with integrated circuit emphasis (SPICE) circuit simulator to simulate VJL SNW FETs with RF parameters extracted from 3D device simulated Y-parameters. We confirmed the validity of our RF model by the well-matched results between HSPICE and 3D device simulation in terms of the Y-parameters and the S_{22}-parameter up to 100 GHz.
- 2012-06-25
著者
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Kang In
School Of Electrical Engineering Seoul National University
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Kim Kyung
School Of Food Biotechnology Woosong University
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Kang In
School of Electronics Engineering, Kyungpook National University, Daegu 702-701, Korea
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Shin Sunhae
School of Electrical and Computer Engineering, Ulsan National Institute of Science and Technology, Ulsan 689-798, Korea
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