Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
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概要
- 論文の詳細を見る
We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-04-15
著者
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Lee Jong
School Of Adv. Mat. Sci. & Eng. Sungkyunkwan Univ.
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Sim Jae
School Of Electrical Engineering & Inter-university Semiconductor Research Center (isrc) Seoul N
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SONG Ki-Whan
School of Electrical Engineering, Seoul National University
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YOU Young
R&D Center, Samsung Electronics Co.
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PARK Joo-On
R&D Center, Samsung Electronics Co.
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JIN You
R&D Center, Samsung Electronics Co.
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KIM Young-Wug
R&D Center, Samsung Electronics Co.
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Kim Kyung
School Of Food Biotechnology Woosong University
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Lee Yong
School Of Bioscience And Biotechnology And Institute Of Bioscience And Biotechnology Kangwon Nationa
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Park Byung-gook
School Of Electrical Engineering And Computer Sciences And The Inter-university Semiconductor Resear
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Lee Yong
School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea
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Kim Kyung
School of Chemical Engineering and Materials Science, Chung-Ang University, 221 Huksuk-dong, Dongjak-gu, Seoul 156-756, Korea
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Park Byung-Gook
School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea
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Park Byung-Gook
School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Korea
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Jin You
R&D Center, Samsung Electronics Co., San#24, Nongseo-ri, Kiheung-eup, Yongin City, Kyungki-do 449-711, Korea
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You Young
R&D Center, Samsung Electronics Co., San#24, Nongseo-ri, Kiheung-eup, Yongin City, Kyungki-do 449-711, Korea
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Kim Young-Wug
R&D Center, Samsung Electronics Co., San#24, Nongseo-ri, Kiheung-eup, Yongin City, Kyungki-do 449-711, Korea
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Park Byung-Gook
School of EECS and ISRC, Seoul National University, Seoul 151-742, Korea
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Kim Kyung
School of Electrical Engineering, Seoul National University, San 56-1, Shinlim-dong, Kwanak-gu, Seoul 151-742, Korea
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