CMOS low-noise amplifer with noise suppression technique from gate resistance (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))

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概要

• 論文の詳細を見る

• In this paper, design and results of a fully integrated 5.8 GHz low noise amplifier (LNA) using 0.13-μm CMOS technology are presented. Commonly adopted inductive source degeneration for input impedance matching is eliminated for smaller chip area while providing reasonable input 50 Ohm matching. With a simple LC-tank structure, the effective inductance of the gate inductor was increased and its size was reduced. Also by adding capacitance between gate and source of the input transistor, a noise source from the gate resistance is partly suppressed. The layout of the LNA occupies total area of 0.7-mm^2 and the results show forward power gain (S_<21>) of 12-dB and noise figure of 3.9-dB while consuming 6.8-mW from a 1.2-V DC supply.

• 社団法人電子情報通信学会の論文
• 2007-06-18

著者

• SONG Ickhyun

  Inter-University Semiconductor Research Center (ISRC) and School of EE, Seoul National University

• Koo Min

  Dept. Of Eecs Seoul National University

• Song Ickhyun

  School Of Electrical Engineering And Computer Science Seoul National University

• Song Ickhyun

  Inter-university Semiconductor Research Center (isrc):school Of Electrical Engineering Seoul Nationa

• Song Ickhyun

  Dept. Of Eecs Seoul National University

• Jhon Hee

  Dept. Of Eecs Seoul National University

• Shin Hyungcheol

  School Of Electrical Engineering And Computer Science Seoul National University

• Shin Hyungcheol

  Dept. Of Eecs Seoul National University

• Shin Hyungcheol

  Dept. Of Eecs Kaist

関連論文

• 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
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• Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4G NAND Flash
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
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• 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
• Non-Quasi-Static Small-Signal Model of RF MOSFETs Valid up to 110GHz
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
• Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
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• CMOS low-noise amplifer with noise suppression technique from gate resistance (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• CMOS low-noise amplifer with noise suppression technique from gate resistance (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
• Improving the Cell Characteristics Using SiN Liner at Active Edge in 4 Gbits NAND Flash Memories
• Simple Wide-Band Metal-Insulator-Metal (MIM) Capacitor Model for RF Applications and Effect of Substrate Grounded Shields
• Highly Manufacturable and Reliable 80-nm Gate Twin Silicon–Oxide–Nitride–Oxide–Silicon Memory Transistor
• Simultaneous Extraction of Locations and Energies of Two Independent Traps in Gate Oxide From Four-Level Random Telegraph Signal Noise
• Characterization of Sensitivity and Resolution of Silicon Resistive Probe

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