FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
スポンサーリンク
概要
- 論文の詳細を見る
As the gate area decreases to the order of a square micron, individual trapping events can be detected as fluctuations between discrete levels of the drain current, known as random telegraph signal (RTS) noise. Many circuit application areas such as CMOS Image sensor and flash memory are already suffering from RTS noise. Especially, in case of flash memory, FN stress causes threshold voltage shift problems due to generation of additional oxide traps, which degrades circuit performance. In this paper, we investigated how FN stress effects on RTS noise behavior in MOSFET and monitored it in both the time domain and frequency domain.
- (社)電子情報通信学会の論文
- 2008-05-01
著者
-
Shin Hyungcheol
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
-
SONG Ickhyun
Inter-University Semiconductor Research Center (ISRC) and School of EE, Seoul National University
-
Song Ickhyun
Inter-university Semiconductor Research Center (isrc) And School Of Ee Seoul National University
-
Song Ickhyun
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
LEE Hochul
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
-
YOON Youngchang
Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Sci
-
Shin Hyungcheol
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
-
Shin Hyungcheol
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
Lee Hochul
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
Yoon Youngchang
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
-
Shin Hyungcheol
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat
-
Shin Hyungcheol
Inter-university Semiconductor Research Center (isrc)
-
Shin Hyungcheol
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
関連論文
- A new cone-type 1T DRAM cell (Electron devices)
- Independent Gate Twin-bit SONOS flash memory with split-gate effect (Silicon devices and materials)
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
- Extraction of Trap Depth in Flash Cell Having Arch-Active Structure
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
- Spatial Distribution of Channel Thermal Noise in Short-Channel MOSFETs
- Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
- Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
- Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
- Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
- 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
- Investigating programming motivation sources from student behavior (教育工学)
- Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
- Low cost CMOS LNA design using thin-metal CMOS process (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Low cost CMOS LNA design using thin-metal CMOS process (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- Accurate Extraction of Mobility, Effective Channel Length, and Source/Drain Resistance in 60nm MOSFETs
- RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- RF Linearity Analysis of FinFETs using 3-D Device Simulation (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))
- 24GHz Low Noise Amplifier Design in 65nm CMOS Technology with Inter-Stage Matching Optimization(Session8B: High-Frequency, Photonic and Sensing Devices)
- Improving Read Disturb Characteristics by Using Double Common Source Line and Dummy Switch Architecture in Multi Level Cell NAND Flash Memory with Low Power Consumption
- Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
- Analysis of random telegraph signal noise in dual and single oxide device and its application to complementary metal oxide semiconductor image sensor readout circuit (Special issue: Solid state devices and materials)
- Analysis of Random Telegraph Signal Noise in Dual and Single Oxide Device And Its Application to CMOS Image Sensor Readout Circuit
- FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- FN stess induced degradation on random telegraph signal noise in deep submicron NMOSFETs (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Accurate Extraction of the Trap Depth From RTS Noise Data By including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
- Implementation of Channel Thermal Noise Model in CMOS RFIC Design(Session8A: Si Devices III)
- Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
- Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
- Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
- Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
- Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
- CMOS low-noise amplifer with noise suppression technique from gate resistance (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- CMOS low-noise amplifer with noise suppression technique from gate resistance (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
- Accurate Extraction of Excess Channel Thermal Noise Coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4
- Dynamic driving current using side gate bias of single-electron transistors
- Extraction of Electron Band Mobility in Amorphous Silicon Thin-Film Transistors
- Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits
- A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device
- Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator
- Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
- Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
- On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale Metal–Oixde–Semiconductor Field Effect Transistors
- An Analytic Current–Voltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance
- L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications
- 16GHz CMOS LNA design without Source degeneration inductor (先端デバイスの基礎と応用に関するアジアワークショップ(AWAD2005))