Self-Aligned Asymmetric Metal–Oxide–Semiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator

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概要

• 論文の詳細を見る

• We have fabricated the sub-30 nm asymmetric n-channel metal–oxide–semiconductor field effect transistors (NMOSFETs) and investigated its operation and characteristics. In this work, two key ideas are newly introduced in order to improve the device performance. One is the introduction of silicon-on-insulator (SOI) substrate to remove junction leakage paths. The other is the modification of mask layout for performance optimization and mass production. By using SOI substrate and modifying mask layout, the ON/OFF current ratio of the fabricated device is quite increased when we compared with the previous work because the source/drain junction leakage and parasitic current are suppressed. Moreover, the fabricated device has excellent scaling properties in terms of short channel effect.

• Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
• 2009-09-25

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Kim Jong

  Inter-university Semiconductor Research Center Seoul National University:school Of Electrical Engine

• Song Jae

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Choi Woo

  Department Of Dermatology Sanggye Paik Hospital Inje University College Of Medicine

• Shin Hyungcheol

  Inter-university Semiconductor Research Center (isrc)

• Kim Sang

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Park Jae

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Park Jae

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

• Kim Jong

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Kim Jong

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

• Kim Sang

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

• Song Jae

  Inter-University Semiconductor Research Center (ISRC)

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Choi Woo

  Department of Electronics Engineering, Sogang University, Seoul 121-742, Korea

• Lee Jong

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

• Shin Hyungcheol

  Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

• CHOI WOO

  Department of Chemical Engineering, Doshisha University

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