Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))

スポンサーリンク

概要

• 論文の詳細を見る

• We have proposed RODOS (Reverse-Order source/drain formation with Double Offset Spacer) for low power and high speed. Simulation is done to evaluate its potential. It shows enhanced performance in terms of poly-depletion effect, DC characteristics, gate delay and switching energy. At 50nm channel length, it demonstrates 794μA/μm in on-current, 0.1nA/μm in off-current, 65mV/V in DIBL, 80mV/dec in SS, 1.29ps in gate delay, 198GHz in f_T and 0.151fJ in switching energy.

• 社団法人電子情報通信学会の論文
• 2003-06-23

著者

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• CHOI Woo

  Inter-University Semiconductor Research Center, Seoul National University

• CHOI Byung

  Inter-University Semiconductor Research Center, Seoul National University

• LEE Jong

  Inter-University Semiconductor Research Center, Seoul National University

• Choi B

  Seoul National Univ. Seoul Kor

• Choi W

  Inter-university Semiconductor Research Center Seoul National University

• Choi Woo

  Inter-university Semiconductor Research Center Seoul National University

• Lee J

  Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

• Woo Dong-soo

  Inter-university Semiconductor Research Center Seoul National University

• Lee Jong

  Inter-univ. Semicon. Res. Center Seoul Nat. Univ.

• Woo Dong-soo

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering Seoul Nat

• Choi Byung

  Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Choi Woo

  Inter-university Semiconductor Research Center and School of Electrical Engineering, Seoul National University, ENG 420-016, Sillim-dong, Gwank-gu, Seoul 151-722, Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

関連論文

• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• A new cone-type 1T DRAM cell (Electron devices)
• Independent Gate Twin-bit SONOS flash memory with split-gate effect (Silicon devices and materials)
• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Nanoscale Multi-Line Patterning Using Sidewall Structure
• Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
• Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
• Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Full-swing pentacene organic inverter with long-channel driver and short-channel load
• A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
• Silicon Quantum Tunneling Devices - FIBTET and MOSET
• Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
• Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
• Channel Doping Engineering with Indium as an Alternative p-Type Dopant
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
• Novel Gate-All-Around MOSFETs with Self-Aligned Structure
• Multi-Functionality of Novel Structured Tunneling Devices
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs
• Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
• Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
• Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• 70nm Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices Using Fowler-Nordheim Programming and Hot Hole Erase Method
• Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
• Non-Quasi-Static Modeling of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor and Its Model Verification up to 1 THz
• Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
• Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
• Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
• Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
• Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process
• Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
• Random Telegraph Signal-Like Fluctuation Created by Fowler–Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor
• Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
• Self-Aligned Dual-Gate Single-Electron Transistors
• Design Guideline of Si-Based L-Shaped Tunneling Field-Effect Transistors
• Novel Protruded-Shape Unipolar Resistive Random Access Memory Structure for Improving Switching Uniformity through Excellent Conductive Filament Controllability
• Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory
• Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics
• Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

もっと見る 閉じる

スポンサーリンク