Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer

スポンサーリンク

概要

• 論文の詳細を見る

• We propose a gate-all-around tunnel field effect transistor (GAA TFET) having a n-doped layer at the source junction and investigate its electrical characteristics with device simulation. By introducing the n-doped layer, band-to-band tunneling area is increased and tunneling barrier width is decreased. Also, electric field induced by gate bias is increased by the surrounding gate structure, which makes it possible to obtain a more abrupt band-bending. These effects bring about a significant improvement in on-current and subthreshold characteristics. GAA TFET with n-doped layer shows subthreshold swing at Id =1nA/µm of 32.5mV/dec, average subthreshold swing of 20.6mV/dec. With comparison to other TFET structures, the merits of the proposed device are demonstrated and performance dependences on device parameters are characterized by extensive simulations.

著者

• LEE Dong

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• YANG Hong-Seon

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• KANG Kwon-Chil

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Joung-Eob

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• LEE Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• CHO Seongjae

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• PARK Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

関連論文

• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• A new cone-type 1T DRAM cell (Electron devices)
• Independent Gate Twin-bit SONOS flash memory with split-gate effect (Silicon devices and materials)
• Side-Gate Design Optimization of 50nm MOSFETs with Electrically Induced Source/Drain
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Nanoscale SONOS Flash Memories(Session B6 Si-Devices II)(2004 Asia-Pacific Workshop on Fundamentals and Application of Advanced Semiconductor Devices (AWAD 2004))
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
• Characteristic of Dual-Gate Single Electron Transistor (DG-SET) with extended channel using shallow doping and sidewall patterning for suppressing MOS current(Session 9B : Nano-Scale devices and Physics)
• Nanoscale Multi-Line Patterning Using Sidewall Structure
• Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology
• Single-Electron Transistors with Sidewall Depletion Gates on a Silicon-On-Insulator Nano-Wire
• Single Electron Memory with a Defined Poly-Si Dot Based on Conventional VLSI Technology
• Room Temperature Coulomb Oscillation of a Single Electron Switch with an Electrically Formed Quantum Dot and Its Modeling
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Design and Simulation of Self-Aligned Vertical Island Single Electron Transistor (VI-SET) with Electrical Tunneling Barrier
• Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Charge Injection Path of Bottom-Contact Organic Thin-Film Transistors(Session4B: Emerging Devices II)
• Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
• 3-dimensional Terraced NAND (3D TNAND) Flash Memory(Session4A: Nonvolatile Memory)
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for room temperature operation(Session3: Emerging Devices I)
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Self-Aligned Dual-Gate Single-Electron Transistors (DG-SETs)
• An Analytic Current-Voltage Equation for Top-contact OTFTs Including the Effects of Variable Series Resistance
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• Pentacene TFTs Fabricated by High-aspect Ratio Metal Shadow Mask
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
• Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
• Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
• Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
• Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
• Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
• Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
• 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
• Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
• Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
• Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
• Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
• Full-swing pentacene organic inverter with long-channel driver and short-channel load
• A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
• Silicon Quantum Tunneling Devices - FIBTET and MOSET
• Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function in the Coulomb-Blockade Oscillation Region
• Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
• Channel Doping Engineering with Indium as an Alternative p-Type Dopant
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Nanoscale Poly-Si Line Formation and Its Uniformity
• Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
• Novel Gate-All-Around MOSFETs with Self-Aligned Structure
• Multi-Functionality of Novel Structured Tunneling Devices
• Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs(Ultra-Thin Gate Insulators,Fundamentals and Applications of Advanced Semiconductor Devices)
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
• Design and Simulation of Asymmetric MOSFETs
• Integration Process of Impact-Ionization Metal-Oxide-Semiconductor Devices with Tunneling Field-Effect-Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors
• Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
• Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
• Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
• Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
• Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
• 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
• Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
• 70nm Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices Using Fowler-Nordheim Programming and Hot Hole Erase Method
• Investigation of Threshold Voltage Disturbance Caused by Programmed Adjacent Cell in Virtual Source/Drain NAND Flash Memory
• Non-Quasi-Static Modeling of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor and Its Model Verification up to 1 THz
• Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
• Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
• Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
• Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
• Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
• Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process
• Silicon-Based Dual-Gate Single-Electron Transistors for Logic Applications
• Plasma Electrolytic Oxidation of AZ91 Mg Alloy in the Sodium Stannate Electrolyte
• Minimization of Gate-Induced Drain Leakage by Controlling Gate Underlap Length for Low-Standby-Power Operation of 20-nm-Level Four-Terminal Silicon-on-Insulator Fin-Shaped Field Effect Transistor
• Dynamic driving current using side gate bias of single-electron transistors
• Self-Aligned Dual-Gate Single-Electron Transistors
• Dual-Gate Single-Electron Transistor with Silicon Nano Wire Channel and Surrounding Side Gates
• Evaluation and Resolution for Nonideal Characteristics of Complementary Metal–Oxide–Semiconductor Devices Fabricated on Silicon-on-Insulator

もっと見る 閉じる

スポンサーリンク