Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory

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概要

• 論文の詳細を見る

• In this paper, arch gate silicon–oxide–nitride–oxide–silicon (SONOS) flash memory is studied. The key technology for this device lies in making the device channel on an arch-shaped silicon fin. This feature enhances the electric field across the tunneling oxide by field concentration, and at the same time, reduces the field across the barrier oxide. Thus, when the high gate voltage is applied in the program operation, the tunneling current, and in turn, the program speed is drastically improved. The lowered electric field at the top oxide prohibits the electron back-tunneling from the polycrystalline silicon gate, which enables more reliable and faster erase operation. Full fabrication processes and the measurement results are presented in detail. The process and device simulation results are also given to confirm the critical electrostatic characteristics of the Arch SONOS flash memory device at each step and design the process integration.

• 2010-11-25

著者

• LEE Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• CHO Seongjae

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Compu

• Yun Jang-gn

  Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

• Park Byung-Gook

  Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Lee Gil

  Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Yun Jang-Gn

  Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Lee Jung

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Lee Jung

  Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Cho Seongjae

  Inter-University Semiconductor Research Center (ISRC) and School of Electrical and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea

• Cho Seongjae

  Inter-university Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-gu, Seoul 151-742, Republic of Korea

• Park Byung-Gook

  Inter-University Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-742, Republic of Korea

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