Yun Jang-gn | Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu

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概要

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著作論文

A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Independent Gate Twin-bit SONOS Flash Memory with Split-gate Effect(Session 8A : Memory 2)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
Fin and Recess-Channel Metal Oxide Semiconductor Field Effect Transistor for Sub-50 nm Dynamic Random Access Memory Cell
Program/Erase Model of Nitride-Based NAND-Type Charge Trap Flash Memories
Room-Temperature Operation of a Single-Electron Transistor Made by Oxidation Process Using the Recessed Channel Structure
Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
Fabrication of Highly Scaled Silicon Nanowire Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors by Using Self-Aligned Local-Channel V-gate by Optical Lithography Process
Extended Word-Line NAND Flash Memory

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