Kim Doo‐hyun | Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci

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概要

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著作論文

Program/erase model of nitride-based NAND-type charge trap flash memories
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
A New 1T DRAM Cell : Cone Type 1T DRAM Cell

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