Program/erase model of nitride-based NAND-type charge trap flash memories
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概要
著者
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Cho Seongjae
Inter-university Semiconductor Research Center (isrc) And School Of Electrical Engineering And Compu
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Kim Doo‐hyun
Inter-university Semiconductor Research Center And School Of Electrical Engineering And Computer Sci
関連論文
- Program/erase model of nitride-based NAND-type charge trap flash memories
- Investigation of field concentration effects in arch gate silicon-oxide-nitride-oxide-silicon flash memory
- Evaluation and resolution for nonideal characteristics of complementary metal-oxide-semiconductor devices fabricated on silicon-on-insulator
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- A New Cone-Type 1T DRAM Cell(Session 2A : Memory 1)
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Study on Dependence of Self-Boosting Channel Potential on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- Design of Vertical Nonvolatile Memory Device Considering Gate-Induced Barrier Lowering (GIBL)(Session4A: Nonvolatile Memory)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Threshold Voltage Roll-off Mechanisms in SONOS Flash Memory in Retention Mode Including Trapped Charge Redistribution Effect(Session 2A : Memory 1)
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Multi-level reading method by using PCI (Paired Cell Interference) in vertical NAND flash memory
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Simulation of Retention Characteristics in Double-Gate Structure Multi-bit SONOS Flash Memory(Session4A: Nonvolatile Memory)
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Establishing read operation bias schemes for 3-D pillar-structure flash memory devices to overcome paired cell interference (PCI) (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices(Novel MOSFET Structures,Fundamentals and Applications of Advanced Semiconductor Devices)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles(Session 7A Silicon Devices IV,AWAD2006)
- Analyses on Current Characteristics of 3-D MOSFET Nonvolatile Memory Devices Determined by Junction Doping Profiles
- Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
- Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- A New 1T DRAM Cell : Cone Type 1T DRAM Cell